Hierarchical Partitioning-Based Inter-Chip Redistribution Layer Routing for Fan-Out Wafer-Level Packaging

In modern advanced fan-out wafer-level packaging (FOWLP), redistribution layers (RDLs) are used to implement efficient interconnections among chips, where both flexible vias and irregular pad structures can be deployed to realize highly integrated heterogeneous systems. With the sharp increase in chip densities, however, it becomes challenging to fully utilize the routing resources in RDLs. The routing graph without optimized resource planning can lead to significant deterioration in the solution quality of RDL design. Furthermore, prior work determines via locations in the RDLs before identifying wire routes, thus offsetting the advantages of flexible vias and irregular pads. To systematically solve the RDL routing problem in FOWLP, in this paper, we propose a hierarchical partitioning-based inter-chip routing method considering both flexible vias and irregular pads, so that optimized RDL solutions can be generated automatically and efficiently. The proposed method includes the following key techniques: 1) a channel planning method for optimized routing region partition and a dynamic routing graph-based pathfinding method for efficient global routing, 2) a binary-search-based hierarchical tile segmentation method for conflict removal and wirelength reduction, 3) a novel monotonicity-analysis-based access point optimization method and a staggered via planning strategy for both wirelength and detour reduction, and 4) a geometry-based detailed routing algorithm for innertile wire routing. The experimental results demonstrate that the proposed algorithm leads to 100% routablility and 4.8% wirelength reduction on average compared to the state-of-the-art work, with a maximum reduction rate of 10.3% across all the benchmarks.