TY - JOUR
T1 - Graph-based techniques to speed up floorplan area optimization
AU - Wang, Ting-Chi
AU - Wong, D. F.
N1 - Funding Information:
This work was partially supported by the National Science Foundation under grant MIP-8909586, by an ACM SIGDA scholarship, and by an IBM Faculty Development Award.
Publisher Copyright:
© 1993 Published by Elsevier B.V.
PY - 1993/10
Y1 - 1993/10
N2 - A well known approach for the floorplan area optimization problem is to first determine a list of all non-redundant implementations of the entire floorplan and then select an optimal floorplan from the list [1-7]. For large floorplans, this approach may fail due to insufficient memory space available to store the implementations of sub-floorplans generated during the computation. An effective method to reduce memory usage is as follows: During the computation, whenever the set of non-redundant implementations of a sub-floorplan exceeds a certain predefined size, we only retain a subset of the implementations that can best approximate the original set. In this paper, we present two algorithms to optimally select implementations for rectangular and L-shaped sub-floorplans. Our algorithms can be applied to existing floorplan area optimization algorithms such as [3-7] to improve their performances. The common key idea of our two algorithms is to reduce the problem of optimally selecting a subset of implementations to a constrained shortest path problem, which we can solve optimally in polynomial time. We have incorporated the two algorithms into [7] and obtained very encouraging experimental results.
AB - A well known approach for the floorplan area optimization problem is to first determine a list of all non-redundant implementations of the entire floorplan and then select an optimal floorplan from the list [1-7]. For large floorplans, this approach may fail due to insufficient memory space available to store the implementations of sub-floorplans generated during the computation. An effective method to reduce memory usage is as follows: During the computation, whenever the set of non-redundant implementations of a sub-floorplan exceeds a certain predefined size, we only retain a subset of the implementations that can best approximate the original set. In this paper, we present two algorithms to optimally select implementations for rectangular and L-shaped sub-floorplans. Our algorithms can be applied to existing floorplan area optimization algorithms such as [3-7] to improve their performances. The common key idea of our two algorithms is to reduce the problem of optimally selecting a subset of implementations to a constrained shortest path problem, which we can solve optimally in polynomial time. We have incorporated the two algorithms into [7] and obtained very encouraging experimental results.
KW - constrained shortest path
KW - floorplan area optimization
KW - Floorplan design
UR - http://www.scopus.com/inward/record.url?scp=0027681976&partnerID=8YFLogxK
U2 - 10.1016/0167-9260(93)90051-D
DO - 10.1016/0167-9260(93)90051-D
M3 - Journal article
AN - SCOPUS:0027681976
SN - 0167-9260
VL - 15
SP - 179
EP - 199
JO - Integration, the VLSI Journal
JF - Integration, the VLSI Journal
IS - 2
ER -