GlitchMap: An FPGA technology mapper for low power considering glitches

Lei Cheng, Deming Chen, Martin D. F. Wong

Research output: Chapter in book/report/conference proceedingConference proceedingpeer-review

22 Citations (Scopus)


In 90-nm technology, dynamic power is still the largest power source in FPGAs [1], and signal glitches contribute a large portion of the dynamic power consumption. Previous poweraware technology mapping algorithms for FPGAs have not taken into account the glitch power reduction. In this paper, we present a dynamic power estimation model and a new technology mapping algorithm considering glitches. To the best of our knowledge, this is the first work that explicitly reduces glitch power during technology mapping for FPGAs. Experiments show that our algorithm, named GlitchMap, is able to reduce dynamic power by 18.7% compared to a previous state-of-the-art power-aware algorithm, EMap [2].

Original languageEnglish
Title of host publication44th ACM/IEEE Design Automation Conference - Proceedings 2007
PublisherAssociation for Computing Machinery (ACM)
Number of pages6
ISBN (Print)9781595936271, 1595936270
Publication statusPublished - 6 Jun 2007
Event44th ACM/IEEE Design Automation Conference, DAC 2007 - San Diego, United States
Duration: 4 Jun 20078 Jun 2007 (Conference website ) (Conference programme ) (Conference proceedings)

Publication series

NameACM/IEEE Design Automation Conference - Proceedings
ISSN (Print)0738-100X


Conference44th ACM/IEEE Design Automation Conference, DAC 2007
Country/TerritoryUnited States
CitySan Diego
Internet address

Scopus Subject Areas

  • Hardware and Architecture
  • Control and Systems Engineering

User-Defined Keywords

  • Dynamic power
  • FPGA technology mapping
  • Glitch


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