GlitchMap: An FPGA technology mapper for low power considering glitches

Lei Cheng; Deming Chen; Martin D. F. Wong

doi:10.1145/1278480.1278562

GlitchMap: An FPGA technology mapper for low power considering glitches

Lei Cheng, Deming Chen, Martin D. F. Wong

Office of the Provost

Research output: Chapter in book/report/conference proceeding › Conference proceeding › peer-review

22 Citations (Scopus)

Abstract

In 90-nm technology, dynamic power is still the largest power source in FPGAs [1], and signal glitches contribute a large portion of the dynamic power consumption. Previous poweraware technology mapping algorithms for FPGAs have not taken into account the glitch power reduction. In this paper, we present a dynamic power estimation model and a new technology mapping algorithm considering glitches. To the best of our knowledge, this is the first work that explicitly reduces glitch power during technology mapping for FPGAs. Experiments show that our algorithm, named GlitchMap, is able to reduce dynamic power by 18.7% compared to a previous state-of-the-art power-aware algorithm, EMap [2].

Original language	English
Title of host publication	44th ACM/IEEE Design Automation Conference - Proceedings 2007
Publisher	Association for Computing Machinery (ACM)
Pages	318-323
Number of pages	6
ISBN (Print)	9781595936271, 1595936270
DOIs	https://doi.org/10.1145/1278480.1278562
Publication status	Published - 6 Jun 2007
Event	44th ACM/IEEE Design Automation Conference, DAC 2007 - San Diego, United States Duration: 4 Jun 2007 → 8 Jun 2007 https://www.dac.com/About/Conference-Archive/44th-DAC-2007 (Conference website ) https://www.dac.com/portals/0/documents/archive/2007/44thfinal.pdf (Conference programme ) https://dl.acm.org/doi/proceedings/10.1145/1278480 (Conference proceedings) https://ieeexplore.ieee.org/xpl/conhome/4261113/proceeding

Publication series

Name	ACM/IEEE Design Automation Conference - Proceedings
ISSN (Print)	0738-100X

Conference

Conference	44th ACM/IEEE Design Automation Conference, DAC 2007
Country/Territory	United States
City	San Diego
Period	4/06/07 → 8/06/07
Internet address	https://www.dac.com/About/Conference-Archive/44th-DAC-2007 (Conference website ) https://www.dac.com/portals/0/documents/archive/2007/44thfinal.pdf (Conference programme ) https://dl.acm.org/doi/proceedings/10.1145/1278480 (Conference proceedings) https://ieeexplore.ieee.org/xpl/conhome/4261113/proceeding

Scopus Subject Areas

Hardware and Architecture
Control and Systems Engineering

User-Defined Keywords

Dynamic power
FPGA technology mapping
Glitch

Access to Document

10.1145/1278480.1278562

Cite this

@inproceedings{ba2a19df317b41779009fe0067daf47d,

title = "GlitchMap: An FPGA technology mapper for low power considering glitches",

abstract = "In 90-nm technology, dynamic power is still the largest power source in FPGAs [1], and signal glitches contribute a large portion of the dynamic power consumption. Previous poweraware technology mapping algorithms for FPGAs have not taken into account the glitch power reduction. In this paper, we present a dynamic power estimation model and a new technology mapping algorithm considering glitches. To the best of our knowledge, this is the first work that explicitly reduces glitch power during technology mapping for FPGAs. Experiments show that our algorithm, named GlitchMap, is able to reduce dynamic power by 18.7% compared to a previous state-of-the-art power-aware algorithm, EMap [2].",

keywords = "Dynamic power, FPGA technology mapping, Glitch",

author = "Lei Cheng and Deming Chen and Wong, {Martin D. F.}",

note = "This work is partially sponsored by Altera Corporation through a research grant. We used machines donated by Intel.; 44th ACM/IEEE Design Automation Conference, DAC 2007 ; Conference date: 04-06-2007 Through 08-06-2007",

year = "2007",

month = jun,

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doi = "10.1145/1278480.1278562",

language = "English",

isbn = "9781595936271",

series = "ACM/IEEE Design Automation Conference - Proceedings",

publisher = "Association for Computing Machinery (ACM)",

pages = "318--323",

booktitle = "44th ACM/IEEE Design Automation Conference - Proceedings 2007",

address = "United States",

url = "https://www.dac.com/About/Conference-Archive/44th-DAC-2007, https://www.dac.com/portals/0/documents/archive/2007/44thfinal.pdf, https://dl.acm.org/doi/proceedings/10.1145/1278480, https://ieeexplore.ieee.org/xpl/conhome/4261113/proceeding",

}

Cheng, L, Chen, D & Wong, MDF 2007, GlitchMap: An FPGA technology mapper for low power considering glitches. in 44th ACM/IEEE Design Automation Conference - Proceedings 2007., 4261198, ACM/IEEE Design Automation Conference - Proceedings, Association for Computing Machinery (ACM), pp. 318-323, 44th ACM/IEEE Design Automation Conference, DAC 2007, San Diego, California, United States, 4/06/07. https://doi.org/10.1145/1278480.1278562

GlitchMap: An FPGA technology mapper for low power considering glitches. / Cheng, Lei; Chen, Deming; Wong, Martin D. F.
44th ACM/IEEE Design Automation Conference - Proceedings 2007. Association for Computing Machinery (ACM), 2007. p. 318-323 4261198 (ACM/IEEE Design Automation Conference - Proceedings).

Research output: Chapter in book/report/conference proceeding › Conference proceeding › peer-review

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AU - Cheng, Lei

AU - Chen, Deming

AU - Wong, Martin D. F.

N1 - This work is partially sponsored by Altera Corporation through a research grant. We used machines donated by Intel.

PY - 2007/6/6

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N2 - In 90-nm technology, dynamic power is still the largest power source in FPGAs [1], and signal glitches contribute a large portion of the dynamic power consumption. Previous poweraware technology mapping algorithms for FPGAs have not taken into account the glitch power reduction. In this paper, we present a dynamic power estimation model and a new technology mapping algorithm considering glitches. To the best of our knowledge, this is the first work that explicitly reduces glitch power during technology mapping for FPGAs. Experiments show that our algorithm, named GlitchMap, is able to reduce dynamic power by 18.7% compared to a previous state-of-the-art power-aware algorithm, EMap [2].

AB - In 90-nm technology, dynamic power is still the largest power source in FPGAs [1], and signal glitches contribute a large portion of the dynamic power consumption. Previous poweraware technology mapping algorithms for FPGAs have not taken into account the glitch power reduction. In this paper, we present a dynamic power estimation model and a new technology mapping algorithm considering glitches. To the best of our knowledge, this is the first work that explicitly reduces glitch power during technology mapping for FPGAs. Experiments show that our algorithm, named GlitchMap, is able to reduce dynamic power by 18.7% compared to a previous state-of-the-art power-aware algorithm, EMap [2].

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KW - FPGA technology mapping

KW - Glitch

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GlitchMap: An FPGA technology mapper for low power considering glitches

Abstract

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