Generating more compactable channel routing solutions

Jingsheng Cong; D. F. Wong

doi:10.1016/0167-9260(90)90036-Z

Generating more compactable channel routing solutions

Jingsheng Cong^*, D. F. Wong

^*Corresponding author for this work

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Research output: Contribution to journal › Journal article › peer-review

3 Citations (Scopus)

Abstract

In this paper we present several powerful techniques which allow us to generate efficiently channel routing solutions which are beneficial to further compaction. Our techniques can be applied to straight track compaction as well as to contour routing compaction, and produce very encouraging results. In particular, for Deutsch's Difficult Example, we obtained a straight track routing solution whose area is 7% less than the best known result after straight track compaction. Our router also generated a routing solution which leads to a very satisfactory result after contour routing compaction.

Original language	English
Pages (from-to)	199-214
Number of pages	16
Journal	Integration, the VLSI Journal
Volume	9
Issue number	2
DOIs	https://doi.org/10.1016/0167-9260(90)90036-Z
Publication status	Published - Apr 1990

Scopus Subject Areas

Software
Hardware and Architecture
Electrical and Electronic Engineering

User-Defined Keywords

algorithms
Channel routing
compaction
VLSI layout design

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10.1016/0167-9260(90)90036-Z

Cite this

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title = "Generating more compactable channel routing solutions",

abstract = "In this paper we present several powerful techniques which allow us to generate efficiently channel routing solutions which are beneficial to further compaction. Our techniques can be applied to straight track compaction as well as to contour routing compaction, and produce very encouraging results. In particular, for Deutsch's Difficult Example, we obtained a straight track routing solution whose area is 7% less than the best known result after straight track compaction. Our router also generated a routing solution which leads to a very satisfactory result after contour routing compaction.",

keywords = "algorithms, Channel routing, compaction, VLSI layout design",

author = "Jingsheng Cong and Wong, {D. F.}",

note = "Funding Information: The first author was partially supported by the National Science Foundation under grant MIP 87-03273, by the Semiconductor Research Cooperation under contract 87-DP-109, and by a grant from General Electric Company. The second author was partially supported by the Texas Advanced Research Program under grant 4096, by the National Science Foundation under grant MIP-8909586, and by an IBM Faculty Development Award.",

year = "1990",

month = apr,

doi = "10.1016/0167-9260(90)90036-Z",

language = "English",

volume = "9",

pages = "199--214",

journal = "Integration, the VLSI Journal",

issn = "0167-9260",

publisher = "Elsevier",

number = "2",

}

TY - JOUR

T1 - Generating more compactable channel routing solutions

AU - Cong, Jingsheng

AU - Wong, D. F.

N1 - Funding Information: The first author was partially supported by the National Science Foundation under grant MIP 87-03273, by the Semiconductor Research Cooperation under contract 87-DP-109, and by a grant from General Electric Company. The second author was partially supported by the Texas Advanced Research Program under grant 4096, by the National Science Foundation under grant MIP-8909586, and by an IBM Faculty Development Award.

PY - 1990/4

Y1 - 1990/4

N2 - In this paper we present several powerful techniques which allow us to generate efficiently channel routing solutions which are beneficial to further compaction. Our techniques can be applied to straight track compaction as well as to contour routing compaction, and produce very encouraging results. In particular, for Deutsch's Difficult Example, we obtained a straight track routing solution whose area is 7% less than the best known result after straight track compaction. Our router also generated a routing solution which leads to a very satisfactory result after contour routing compaction.

AB - In this paper we present several powerful techniques which allow us to generate efficiently channel routing solutions which are beneficial to further compaction. Our techniques can be applied to straight track compaction as well as to contour routing compaction, and produce very encouraging results. In particular, for Deutsch's Difficult Example, we obtained a straight track routing solution whose area is 7% less than the best known result after straight track compaction. Our router also generated a routing solution which leads to a very satisfactory result after contour routing compaction.

KW - algorithms

KW - Channel routing

KW - compaction

KW - VLSI layout design

UR - http://www.scopus.com/inward/record.url?scp=0025417581&partnerID=8YFLogxK

U2 - 10.1016/0167-9260(90)90036-Z

DO - 10.1016/0167-9260(90)90036-Z

M3 - Journal article

AN - SCOPUS:0025417581

SN - 0167-9260

VL - 9

SP - 199

EP - 214

JO - Integration, the VLSI Journal

JF - Integration, the VLSI Journal

IS - 2

ER -

Generating more compactable channel routing solutions

Abstract

Scopus Subject Areas

User-Defined Keywords

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