Floorplanning with power supply noise avoidance

Hung Ming Chen; Li Da Huang; I Min Liu; Minghorng Lai; D. F. Wong

doi:10.1145/1119772.1119857

Floorplanning with power supply noise avoidance

Hung Ming Chen, Li Da Huang, I Min Liu, Minghorng Lai, D. F. Wong

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Research output: Chapter in book/report/conference proceeding › Conference proceeding › peer-review

14 Citations (Scopus)

Abstract

With today's advanced integrated circuits (ICs) manufacturing technology in deep submicron (DSM) environment, we can integrate entire electronic systems on a single chip (SoC). However, without careful power supply planning in layout, the design of chips will suffer from mostly signal integrity problems including IR-drop, ΔI noise, and IC reliability. Postroute methodologies in solving signal integrity problem have been applied but they will cause a long turn-around time, which adds costly delays to time-to-market. In this paper, we study the problem of power supply noise avoidance as early as in floorplanning stage. We show that the noise avoidance in power supply planning problem can be formulated as a constrained maximum flow problem and present an efficient yet effective heuristic to handle the problem. Experimental results are encouraging. With slight increase of total wirelength, we achieve almost no-IR-drop requirement violation and 46.6% of improvement on ΔI noise constraint violation compared with a previous approach.

Original language	English
Title of host publication	ASP-DAC '03
Subtitle of host publication	Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Place of Publication	United States
Publisher	Association for Computing Machinery (ACM)
Pages	427-430
Number of pages	4
ISBN (Print)	9780780376601
DOIs	https://doi.org/10.1145/1119772.1119857
Publication status	Published - Jan 2003
Event	8th Asia and South Pacific Design Automation Conference, ASP-DAC 2003 - Kitakyushu, Japan Duration: 21 Jan 2003 → 24 Jan 2003 https://www.aspdac.com/2003/ (Conference website) https://dl.acm.org/doi/proceedings/10.1145/1119772 (Conference proceedings)

Publication series

Name	Proceedings of The Asia and South Pacific Design Automation Conference, ASP-DAC
ISSN (Print)	2153-6961
ISSN (Electronic)	2153-697X

Conference

Conference	8th Asia and South Pacific Design Automation Conference, ASP-DAC 2003
Country/Territory	Japan
City	Kitakyushu
Period	21/01/03 → 24/01/03
Internet address	https://www.aspdac.com/2003/ (Conference website) https://dl.acm.org/doi/proceedings/10.1145/1119772 (Conference proceedings)

Access to Document

10.1145/1119772.1119857

Cite this

Chen, H. M., Huang, L. D., Liu, I. M., Lai, M., & Wong, D. F. (2003). Floorplanning with power supply noise avoidance. In ASP-DAC '03: Proceedings of the 2003 Asia and South Pacific Design Automation Conference (pp. 427-430). (Proceedings of The Asia and South Pacific Design Automation Conference, ASP-DAC). Association for Computing Machinery (ACM). https://doi.org/10.1145/1119772.1119857

@inproceedings{cc470ce63eb94f4eb90300405b2b0d5d,

title = "Floorplanning with power supply noise avoidance",

abstract = "With today's advanced integrated circuits (ICs) manufacturing technology in deep submicron (DSM) environment, we can integrate entire electronic systems on a single chip (SoC). However, without careful power supply planning in layout, the design of chips will suffer from mostly signal integrity problems including IR-drop, ΔI noise, and IC reliability. Postroute methodologies in solving signal integrity problem have been applied but they will cause a long turn-around time, which adds costly delays to time-to-market. In this paper, we study the problem of power supply noise avoidance as early as in floorplanning stage. We show that the noise avoidance in power supply planning problem can be formulated as a constrained maximum flow problem and present an efficient yet effective heuristic to handle the problem. Experimental results are encouraging. With slight increase of total wirelength, we achieve almost no-IR-drop requirement violation and 46.6% of improvement on ΔI noise constraint violation compared with a previous approach.",

author = "Chen, {Hung Ming} and Huang, {Li Da} and Liu, {I Min} and Minghorng Lai and Wong, {D. F.}",

note = "Funding information: This work was partially supported by the National Science Foundation under grant CCR-0244236. Publisher copyright: {\textcopyright} 2003 ACM; 8th Asia and South Pacific Design Automation Conference, ASP-DAC 2003 ; Conference date: 21-01-2003 Through 24-01-2003",

year = "2003",

month = jan,

doi = "10.1145/1119772.1119857",

language = "English",

isbn = "9780780376601",

series = "Proceedings of The Asia and South Pacific Design Automation Conference, ASP-DAC",

publisher = "Association for Computing Machinery (ACM)",

pages = "427--430",

booktitle = "ASP-DAC '03",

address = "United States",

url = "https://www.aspdac.com/2003/, https://dl.acm.org/doi/proceedings/10.1145/1119772",

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Chen, HM, Huang, LD, Liu, IM, Lai, M & Wong, DF 2003, Floorplanning with power supply noise avoidance. in ASP-DAC '03: Proceedings of the 2003 Asia and South Pacific Design Automation Conference. Proceedings of The Asia and South Pacific Design Automation Conference, ASP-DAC, Association for Computing Machinery (ACM), United States, pp. 427-430, 8th Asia and South Pacific Design Automation Conference, ASP-DAC 2003, Kitakyushu, Japan, 21/01/03. https://doi.org/10.1145/1119772.1119857

Floorplanning with power supply noise avoidance. / Chen, Hung Ming; Huang, Li Da; Liu, I Min et al.
ASP-DAC '03: Proceedings of the 2003 Asia and South Pacific Design Automation Conference. United States: Association for Computing Machinery (ACM), 2003. p. 427-430 (Proceedings of The Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in book/report/conference proceeding › Conference proceeding › peer-review

TY - GEN

T1 - Floorplanning with power supply noise avoidance

AU - Chen, Hung Ming

AU - Huang, Li Da

AU - Liu, I Min

AU - Lai, Minghorng

AU - Wong, D. F.

PY - 2003/1

Y1 - 2003/1

N2 - With today's advanced integrated circuits (ICs) manufacturing technology in deep submicron (DSM) environment, we can integrate entire electronic systems on a single chip (SoC). However, without careful power supply planning in layout, the design of chips will suffer from mostly signal integrity problems including IR-drop, ΔI noise, and IC reliability. Postroute methodologies in solving signal integrity problem have been applied but they will cause a long turn-around time, which adds costly delays to time-to-market. In this paper, we study the problem of power supply noise avoidance as early as in floorplanning stage. We show that the noise avoidance in power supply planning problem can be formulated as a constrained maximum flow problem and present an efficient yet effective heuristic to handle the problem. Experimental results are encouraging. With slight increase of total wirelength, we achieve almost no-IR-drop requirement violation and 46.6% of improvement on ΔI noise constraint violation compared with a previous approach.

AB - With today's advanced integrated circuits (ICs) manufacturing technology in deep submicron (DSM) environment, we can integrate entire electronic systems on a single chip (SoC). However, without careful power supply planning in layout, the design of chips will suffer from mostly signal integrity problems including IR-drop, ΔI noise, and IC reliability. Postroute methodologies in solving signal integrity problem have been applied but they will cause a long turn-around time, which adds costly delays to time-to-market. In this paper, we study the problem of power supply noise avoidance as early as in floorplanning stage. We show that the noise avoidance in power supply planning problem can be formulated as a constrained maximum flow problem and present an efficient yet effective heuristic to handle the problem. Experimental results are encouraging. With slight increase of total wirelength, we achieve almost no-IR-drop requirement violation and 46.6% of improvement on ΔI noise constraint violation compared with a previous approach.

U2 - 10.1145/1119772.1119857

DO - 10.1145/1119772.1119857

M3 - Conference proceeding

SN - 9780780376601

T3 - Proceedings of The Asia and South Pacific Design Automation Conference, ASP-DAC

SP - 427

EP - 430

BT - ASP-DAC '03

PB - Association for Computing Machinery (ACM)

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T2 - 8th Asia and South Pacific Design Automation Conference, ASP-DAC 2003

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Chen HM, Huang LD, Liu IM, Lai M, Wong DF. Floorplanning with power supply noise avoidance. In ASP-DAC '03: Proceedings of the 2003 Asia and South Pacific Design Automation Conference. United States: Association for Computing Machinery (ACM). 2003. p. 427-430. (Proceedings of The Asia and South Pacific Design Automation Conference, ASP-DAC). doi: 10.1145/1119772.1119857

Floorplanning with power supply noise avoidance

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