Floorplan design of VLSI circuits

D. F. Wong; C. L. Liu

doi:10.1007/BF01553890

Floorplan design of VLSI circuits

D. F. Wong, C. L. Liu

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47 Citations (Scopus)

Abstract

In this paper we present two algorithms for the floorplan design problem. The algorithms are quite similar in spirit. They both use Polish expressions to represent floorplans and employ the search method of simulated annealing. The first algorithm is for the case where all modules are rectangular, and the second one is for the case where the modules are either rectangular or L-shaped. Our algorithms consider simultaneously the interconnection information as well as the area and shape information for the modules. Experimental results indicate that our algorithms perform well for many test problems.

Original language	English
Pages (from-to)	263-291
Number of pages	29
Journal	Algorithmica
Volume	4
Issue number	1-4
DOIs	https://doi.org/10.1007/BF01553890
Publication status	Published - Jun 1989

Scopus Subject Areas

General Computer Science
Computer Science Applications
Applied Mathematics

User-Defined Keywords

Floorplan design
Simulated annealing
VLSI circuit layout

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10.1007/BF01553890

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title = "Floorplan design of VLSI circuits",

abstract = "In this paper we present two algorithms for the floorplan design problem. The algorithms are quite similar in spirit. They both use Polish expressions to represent floorplans and employ the search method of simulated annealing. The first algorithm is for the case where all modules are rectangular, and the second one is for the case where the modules are either rectangular or L-shaped. Our algorithms consider simultaneously the interconnection information as well as the area and shape information for the modules. Experimental results indicate that our algorithms perform well for many test problems.",

keywords = "Floorplan design, Simulated annealing, VLSI circuit layout",

author = "Wong, {D. F.} and Liu, {C. L.}",

note = "This work was partially supported by the Semiconductor Research Corporation under Contract 86-12-109, by the National Science Foundation under Grant MIP 8703273, and by a grant from the General Electric Company.",

year = "1989",

month = jun,

doi = "10.1007/BF01553890",

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journal = "Algorithmica",

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T1 - Floorplan design of VLSI circuits

AU - Wong, D. F.

AU - Liu, C. L.

N1 - This work was partially supported by the Semiconductor Research Corporation under Contract 86-12-109, by the National Science Foundation under Grant MIP 8703273, and by a grant from the General Electric Company.

PY - 1989/6

Y1 - 1989/6

N2 - In this paper we present two algorithms for the floorplan design problem. The algorithms are quite similar in spirit. They both use Polish expressions to represent floorplans and employ the search method of simulated annealing. The first algorithm is for the case where all modules are rectangular, and the second one is for the case where the modules are either rectangular or L-shaped. Our algorithms consider simultaneously the interconnection information as well as the area and shape information for the modules. Experimental results indicate that our algorithms perform well for many test problems.

AB - In this paper we present two algorithms for the floorplan design problem. The algorithms are quite similar in spirit. They both use Polish expressions to represent floorplans and employ the search method of simulated annealing. The first algorithm is for the case where all modules are rectangular, and the second one is for the case where the modules are either rectangular or L-shaped. Our algorithms consider simultaneously the interconnection information as well as the area and shape information for the modules. Experimental results indicate that our algorithms perform well for many test problems.

KW - Floorplan design

KW - Simulated annealing

KW - VLSI circuit layout

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DO - 10.1007/BF01553890

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VL - 4

SP - 263

EP - 291

JO - Algorithmica

JF - Algorithmica

IS - 1-4

ER -

Floorplan design of VLSI circuits

Abstract

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