Floorplan design for multi-million gate FPGAs

Lei Cheng; Martin D. F. Wong

doi:10.1109/ICCAD.2004.1382589

Floorplan design for multi-million gate FPGAs

Lei Cheng, Martin D. F. Wong

Office of the Provost

Research output: Chapter in book/report/conference proceeding › Conference proceeding › peer-review

23 Citations (Scopus)

Abstract

Modern FPGAs have multi-millions of gates and future generations of FPGAs will be even more complex. This means floorplanning tools will soon be extremely important for the physical design of FPGAs. Due to the heterogeneous logic and routing resources on an FPGA, FPGA floorplanning is very different from the traditional floorplanning for ASICs. This paper presents the first FPGA floorplanning algorithm targeted for FPGAs with heterogeneous resources (e.g., Xilinx's Spartan3 chips consisting of columns of CLBs, RAM blocks, and multiplier blocks). Our algorithm can generate floorplans for Xilinx's XC3S5000 architecture (largest of the Spartan3 family) in a few minutes.

Original language	English
Title of host publication	Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2004
Place of Publication	United States
Publisher	IEEE
Pages	292-299
Number of pages	8
ISBN (Print)	0780387023
DOIs	https://doi.org/10.1109/ICCAD.2004.1382589
Publication status	Published - Nov 2004
Event	IEEE/ACM International Conference on Computer-Aided Design: Digest, ICCAD 2004 - DoubleTree Hotel, San Jose, United States Duration: 7 Nov 2004 → 11 Nov 2004 https://ieeexplore.ieee.org/xpl/conhome/9494/proceeding (Conference proceedings)

Publication series

Name	Proceedings of IEEE/ACM International Conference on Computer-Aided Design, ICCAD
ISSN (Print)	1092-3152

Conference

Conference	IEEE/ACM International Conference on Computer-Aided Design: Digest, ICCAD 2004
Country/Territory	United States
City	San Jose
Period	7/11/04 → 11/11/04
Internet address	https://ieeexplore.ieee.org/xpl/conhome/9494/proceeding (Conference proceedings)

Scopus Subject Areas

Software
Computer Science Applications
Computer Graphics and Computer-Aided Design

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10.1109/ICCAD.2004.1382589

Cite this

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title = "Floorplan design for multi-million gate FPGAs",

abstract = "Modern FPGAs have multi-millions of gates and future generations of FPGAs will be even more complex. This means floorplanning tools will soon be extremely important for the physical design of FPGAs. Due to the heterogeneous logic and routing resources on an FPGA, FPGA floorplanning is very different from the traditional floorplanning for ASICs. This paper presents the first FPGA floorplanning algorithm targeted for FPGAs with heterogeneous resources (e.g., Xilinx's Spartan3 chips consisting of columns of CLBs, RAM blocks, and multiplier blocks). Our algorithm can generate floorplans for Xilinx's XC3S5000 architecture (largest of the Spartan3 family) in a few minutes.",

author = "Lei Cheng and Wong, {Martin D. F.}",

note = "Funding information: This work was partially supported by the National Science Foundation under grants CCR-0244236 and CCR-0306244. Publisher copyright: {\textcopyright} 2004 IEEE.; IEEE/ACM International Conference on Computer-Aided Design: Digest, ICCAD 2004 ; Conference date: 07-11-2004 Through 11-11-2004",

year = "2004",

month = nov,

doi = "10.1109/ICCAD.2004.1382589",

language = "English",

isbn = "0780387023",

series = "Proceedings of IEEE/ACM International Conference on Computer-Aided Design, ICCAD",

publisher = "IEEE",

pages = "292--299",

booktitle = "Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2004",

address = "United States",

url = "https://ieeexplore.ieee.org/xpl/conhome/9494/proceeding",

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Cheng, L & Wong, MDF 2004, Floorplan design for multi-million gate FPGAs. in Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2004. Proceedings of IEEE/ACM International Conference on Computer-Aided Design, ICCAD, IEEE, United States, pp. 292-299, IEEE/ACM International Conference on Computer-Aided Design: Digest, ICCAD 2004, San Jose, California, United States, 7/11/04. https://doi.org/10.1109/ICCAD.2004.1382589

Floorplan design for multi-million gate FPGAs. / Cheng, Lei; Wong, Martin D. F.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2004. United States: IEEE, 2004. p. 292-299 (Proceedings of IEEE/ACM International Conference on Computer-Aided Design, ICCAD).

Research output: Chapter in book/report/conference proceeding › Conference proceeding › peer-review

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Floorplan design for multi-million gate FPGAs

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