TY - JOUR
T1 - FastPass
T2 - A Fast Pin Access Analysis Framework for Detailed Routability Enhancement
AU - Wang, Fangzhou
AU - Liu, Jinwei
AU - Lau, Wing Ho
AU - Li, Haocheng
AU - Young, Evangeline F.Y.
N1 - Publisher Copyright:
© 1982-2012 IEEE.
This work was supported in part by the Grant from the Research Grants Council of the Hong Kong Special Administrative Region, China, under Project CUHK 14209320
PY - 2024/5/1
Y1 - 2024/5/1
N2 - Pin access analysis is a critical step in detailed routing, one of the most complicated stages in the very-large-scale integration (VLSI) physical design flow. In numerous physical design scenarios, where intricate design rules and pin shapes are involved, there is a growing need for efficient and precise evaluation of pin accessibility. Therefore, we introduce FastPass, an improved framework for fast and accurate pin access analysis. FastPass begins by generating pin access routes that adhere to design rules. After that, FastPass preprocesses the conflicts between routes and then employs incremental SAT solving to determine an optimized scheme for pin access. We further integrate FastPass into Dr. CU, a state-of-the-art detailed router to validate its effectiveness. Experimental results on the ISPD 2018 Initial Detailed Routing Contest Benchmark suite show that FastPass can generate design rule checking (DRC)-clean pin access schemes for all cases while being an order of magnitude faster than the known best- acrlong PAAF. With the integration of FastPass, Dr. CU is able to produce detailed routing results with much less short area and fewer DRC violations.
AB - Pin access analysis is a critical step in detailed routing, one of the most complicated stages in the very-large-scale integration (VLSI) physical design flow. In numerous physical design scenarios, where intricate design rules and pin shapes are involved, there is a growing need for efficient and precise evaluation of pin accessibility. Therefore, we introduce FastPass, an improved framework for fast and accurate pin access analysis. FastPass begins by generating pin access routes that adhere to design rules. After that, FastPass preprocesses the conflicts between routes and then employs incremental SAT solving to determine an optimized scheme for pin access. We further integrate FastPass into Dr. CU, a state-of-the-art detailed router to validate its effectiveness. Experimental results on the ISPD 2018 Initial Detailed Routing Contest Benchmark suite show that FastPass can generate design rule checking (DRC)-clean pin access schemes for all cases while being an order of magnitude faster than the known best- acrlong PAAF. With the integration of FastPass, Dr. CU is able to produce detailed routing results with much less short area and fewer DRC violations.
KW - Boolean satisfiability
KW - detailed routing
KW - physical design
KW - Pin access analysis
UR - http://www.scopus.com/inward/record.url?scp=85181570317&partnerID=8YFLogxK
UR - https://ieeexplore.ieee.org/document/10373411
U2 - 10.1109/TCAD.2023.3346302
DO - 10.1109/TCAD.2023.3346302
M3 - Journal article
AN - SCOPUS:85181570317
SN - 0278-0070
VL - 43
SP - 1566
EP - 1579
JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IS - 5
ER -
