Faster and more accurate wiring evaluation in interconnect-centric floorplanning

Hung Ming Chen, D. F. Wong, Wai Kei Mak, Hannah H. Yang

Research output: Chapter in book/report/conference proceedingConference proceedingpeer-review

1 Citation (Scopus)


In deep submicron (DSM) era, the communication between different components is increasing significantly. It is not uncommon to see floorplanning problems with a relatively small number of blocks (e.g., 50) but has a large number of nets (e.g. 20K). Since existing floorplanning algorithms use simulated annelaing which needs to examine a large number of floorplans, the increasing number of nets has made interconnect-centric floorplanning computaionally very expensive. Moreover, there is almost no systematic way to resolve the congestion problem in such magnitude of number of nets in a given floorplan. In this paper, we present a simple yet effective idea to significantly reduce the runtime of interconnect-centric florplanning algorithms. Our idea is to group common nets between two blocks into a single net. This faster wiring evaluation technique is very effective. We also present a more accurate global router for wiring evaluation based on Lagrangian Relaxation. The new router helps further congestion reduction while doing interconnect planning in floorplanning. We have incorporated our algorithms into [2] and observed dramatic improvement in runtime. For a 33-block 15K-net problem, we reduced runtime from over 23 hours to less than 50 minutes.
Original languageEnglish
Title of host publicationGLSVLSI '01
Subtitle of host publicationProceedings of the 11th Great Lakes symposium on VLSI
PublisherAssociation for Computing Machinery (ACM)
Number of pages6
Publication statusPublished - Mar 2001
Event11th Great Lakes Symposium on VLSI, GLSVLSI 2001 - West Lafayette, United States
Duration: 22 Mar 200123 Mar 2001 (Conference proceedings)

Publication series

NameProceedings of the Great Lakes symposium on VLSI, GLSVLSI


Symposium11th Great Lakes Symposium on VLSI, GLSVLSI 2001
Country/TerritoryUnited States
CityWest Lafayette
Internet address

Scopus Subject Areas

  • Electrical and Electronic Engineering


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