Fast placement optimization of power supply pads

Yu Zhong; Martin D. F. Wong

doi:10.1109/ASPDAC.2007.358081

Fast placement optimization of power supply pads

Yu Zhong, Martin D. F. Wong

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Research output: Chapter in book/report/conference proceeding › Conference proceeding › peer-review

19 Citations (Scopus)

Abstract

Power grid networks in VLSI circuits are required to provide adequate input supply to ensure reliable performance. In this paper, we propose algorithms to find the placement of power pads that minimize not only the worst voltage drop but also the voltage deviation across the power grid. Our algorithm uses simulated annealing to minimize the total cost of voltage drops. The key enabler for efficient optimization is a fast localized node-based iterative method to compute the voltages after each movement of pads. Experimental results show that our algorithm demonstrates good runtime characteristics for power grids with large numbers of pad candidates in multi-million-size circuits. For a 16-million-node power grid with 646 thousand pad candidates, our algorithm took 72 minutes to improve the worst voltage drop from 0.398V to 0.196V and reduce the deviation of voltages on the power grid from 0.134V to 0.024V.

Original language	English
Title of host publication	Proceedings of The 12th Asia and South Pacific Design Automation Conference, ASP-DAC 2007
Publisher	IEEE
Pages	763-767
Number of pages	5
ISBN (Print)	9781424406296, 1424406293
DOIs	https://doi.org/10.1109/ASPDAC.2007.358081
Publication status	Published - 26 Jan 2007
Event	12th Asia and South Pacific Design Automation Conference, ASP-DAC 2007 - Pacifico Yokohama, Yokohama, Japan Duration: 23 Jan 2007 → 26 Jan 2007 https://www.aspdac.com/aspdac2007/ (Conference website) https://www.aspdac.com/aspdac2007/pdf/aspdac2007advprog.pdf (Conference programme) https://ieeexplore.ieee.org/xpl/conhome/4195969/proceeding (Conference proceedings)

Publication series

Name	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
ISSN (Print)	2153-6961
ISSN (Electronic)	2153-697X

Conference

Conference	12th Asia and South Pacific Design Automation Conference, ASP-DAC 2007
Country/Territory	Japan
City	Yokohama
Period	23/01/07 → 26/01/07
Internet address	https://www.aspdac.com/aspdac2007/ (Conference website) https://www.aspdac.com/aspdac2007/pdf/aspdac2007advprog.pdf (Conference programme) https://ieeexplore.ieee.org/xpl/conhome/4195969/proceeding (Conference proceedings)

Scopus Subject Areas

Computer Science Applications
Computer Graphics and Computer-Aided Design
Electrical and Electronic Engineering

Access to Document

10.1109/ASPDAC.2007.358081

Cite this

@inproceedings{4e5affd790394e229e1c251cc76d9e66,

title = "Fast placement optimization of power supply pads",

abstract = "Power grid networks in VLSI circuits are required to provide adequate input supply to ensure reliable performance. In this paper, we propose algorithms to find the placement of power pads that minimize not only the worst voltage drop but also the voltage deviation across the power grid. Our algorithm uses simulated annealing to minimize the total cost of voltage drops. The key enabler for efficient optimization is a fast localized node-based iterative method to compute the voltages after each movement of pads. Experimental results show that our algorithm demonstrates good runtime characteristics for power grids with large numbers of pad candidates in multi-million-size circuits. For a 16-million-node power grid with 646 thousand pad candidates, our algorithm took 72 minutes to improve the worst voltage drop from 0.398V to 0.196V and reduce the deviation of voltages on the power grid from 0.134V to 0.024V.",

author = "Yu Zhong and Wong, {Martin D. F.}",

note = "This work was partially supported by the National Science Foundation under grant CCR-0306244.; 12th Asia and South Pacific Design Automation Conference, ASP-DAC 2007 ; Conference date: 23-01-2007 Through 26-01-2007",

year = "2007",

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day = "26",

doi = "10.1109/ASPDAC.2007.358081",

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series = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",

publisher = "IEEE",

pages = "763--767",

booktitle = "Proceedings of The 12th Asia and South Pacific Design Automation Conference, ASP-DAC 2007",

address = "United States",

url = "https://www.aspdac.com/aspdac2007/, https://www.aspdac.com/aspdac2007/pdf/aspdac2007advprog.pdf, https://ieeexplore.ieee.org/xpl/conhome/4195969/proceeding",

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Zhong, Y & Wong, MDF 2007, Fast placement optimization of power supply pads. in Proceedings of The 12th Asia and South Pacific Design Automation Conference, ASP-DAC 2007. Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, IEEE, pp. 763-767, 12th Asia and South Pacific Design Automation Conference, ASP-DAC 2007, Yokohama, Japan, 23/01/07. https://doi.org/10.1109/ASPDAC.2007.358081

Fast placement optimization of power supply pads. / Zhong, Yu; Wong, Martin D. F.
Proceedings of The 12th Asia and South Pacific Design Automation Conference, ASP-DAC 2007. IEEE, 2007. p. 763-767 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in book/report/conference proceeding › Conference proceeding › peer-review

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T1 - Fast placement optimization of power supply pads

AU - Zhong, Yu

AU - Wong, Martin D. F.

N1 - This work was partially supported by the National Science Foundation under grant CCR-0306244.

PY - 2007/1/26

Y1 - 2007/1/26

N2 - Power grid networks in VLSI circuits are required to provide adequate input supply to ensure reliable performance. In this paper, we propose algorithms to find the placement of power pads that minimize not only the worst voltage drop but also the voltage deviation across the power grid. Our algorithm uses simulated annealing to minimize the total cost of voltage drops. The key enabler for efficient optimization is a fast localized node-based iterative method to compute the voltages after each movement of pads. Experimental results show that our algorithm demonstrates good runtime characteristics for power grids with large numbers of pad candidates in multi-million-size circuits. For a 16-million-node power grid with 646 thousand pad candidates, our algorithm took 72 minutes to improve the worst voltage drop from 0.398V to 0.196V and reduce the deviation of voltages on the power grid from 0.134V to 0.024V.

AB - Power grid networks in VLSI circuits are required to provide adequate input supply to ensure reliable performance. In this paper, we propose algorithms to find the placement of power pads that minimize not only the worst voltage drop but also the voltage deviation across the power grid. Our algorithm uses simulated annealing to minimize the total cost of voltage drops. The key enabler for efficient optimization is a fast localized node-based iterative method to compute the voltages after each movement of pads. Experimental results show that our algorithm demonstrates good runtime characteristics for power grids with large numbers of pad candidates in multi-million-size circuits. For a 16-million-node power grid with 646 thousand pad candidates, our algorithm took 72 minutes to improve the worst voltage drop from 0.398V to 0.196V and reduce the deviation of voltages on the power grid from 0.134V to 0.024V.

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Fast placement optimization of power supply pads

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