Fast performance-driven optimization for buffered clock trees based on Lagrangian relaxation

Chung-Ping Chen, Yao-Wen Chang, D. F. Wong

Research output: Chapter in book/report/conference proceedingChapterpeer-review

24 Citations (Scopus)


Delay, power, skew, area, and sensitivity are the most important concerns in current clock-tree design. We present in this paper an algorithm for simultaneously optimizing the above objectives by sizing wires and buffers in clock trees. Our algorithm, based on Lagrangian relaxation method, can optimally minimize delay, power, and area simultaneously with very low skew and sensitivity. With linear storage overall and linear runtime per iteration, our algorithm is extremely economical, fast, and accurate; for example, our algorithm can solve a 6201-wire-segment clock-tree problem using about 1-minute runtime and 1.3-MB memory and still achieve pico-second precision on an IBM RS/6000 workstation.

Original languageEnglish
Title of host publication33rd ACM/IEEE Design Automation Conference - Proceedings 1996
PublisherAssociation for Computing Machinery (ACM)
Number of pages4
ISBN (Print)9780897917797, 0780332946
Publication statusPublished - Jun 1996
Event33rd ACM/IEEE Design Automation Conference, DAC 1996 - Las Vegas, United States
Duration: 3 Jun 19967 Jun 1996 (Link to conference proceedings)

Publication series

NameACM/IEEE Design Automation Conference - Proceedings
ISSN (Print)0738-100X


Conference33rd ACM/IEEE Design Automation Conference, DAC 1996
Country/TerritoryUnited States
CityLas Vegas
Internet address

Scopus Subject Areas

  • Hardware and Architecture
  • Control and Systems Engineering


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