Common-path-pessimism removal (CPPR) is a pivotal step to achieve accurate timing signoff. Unnecessary pessimism might arise quality-of-result (QoR) concerns such as reporting worse violations than the true timing properties owned by the physical circuit. In other words, signoff timing report will conclude a lower clock frequency at which circuits can operate than actual silicon implementations. Therefore, we introduce in this paper a fast path-based timing analysis for CPPR. Unlike existing approaches which are dominated by explicit path search, we perform implicit path representation which yields significantly smaller search space and faster runtime. Specifically, our algorithm is superior in both space and time saving, from which the memory storage and important timing quantities are available in constant space and constant time per path during the search. Experimental results on industrial benchmarks released from TAU 2014 timing analysis contest have shown that our algorithm won the first place and achieved the best result in terms of accuracy and runtime over all participating teams.
|Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
|2014 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2014
|2/11/14 → 6/11/14