TY - JOUR
T1 - Exploring Rule-Free Layout Decomposition via Deep Reinforcement Learning
AU - Jiang, Bentian
AU - Zang, Xinshi
AU - Wong, Martin D.F.
AU - Young, Evangeline F.Y.
N1 - Funding Information:
This work was supported in part by the Research Grants Council of the Hong Kong, SAR, under Project CUHK 14209320
Publisher Copyright:
© 2022 IEEE.
PY - 2023/9
Y1 - 2023/9
N2 - Multiple patterning lithography decomposition (MPLD) and mask optimization enable the ever-shrinking device feature sizes far below the lithography system limit. Conventional MPLD is solved by mathematical programming or graph-based approaches, where a set of predetermined rules is indispensable to identify the conflicts to be resolved. In this article, we explore rule-free layout decomposition following a simple but sweet principle, let the mask optimizer 'teach' the layout decomposer how to generate suitable decompositions. Our flow includes a reinforcement-learning-based layout decomposer and a deep-learning-based mask optimizer. Without any handcrafted rules, our framework can perform competitively and even surpass the state-of-the-art rule-based methods with notable (7×∼ 63×) turn-around-time speedup.
AB - Multiple patterning lithography decomposition (MPLD) and mask optimization enable the ever-shrinking device feature sizes far below the lithography system limit. Conventional MPLD is solved by mathematical programming or graph-based approaches, where a set of predetermined rules is indispensable to identify the conflicts to be resolved. In this article, we explore rule-free layout decomposition following a simple but sweet principle, let the mask optimizer 'teach' the layout decomposer how to generate suitable decompositions. Our flow includes a reinforcement-learning-based layout decomposer and a deep-learning-based mask optimizer. Without any handcrafted rules, our framework can perform competitively and even surpass the state-of-the-art rule-based methods with notable (7×∼ 63×) turn-around-time speedup.
KW - Design for manufacturability
KW - double patterning
KW - inverse lithography technique (ILT)
KW - reinforcement learning (RL)
UR - http://www.scopus.com/inward/record.url?scp=85146252491&partnerID=8YFLogxK
U2 - 10.1109/TCAD.2022.3232992
DO - 10.1109/TCAD.2022.3232992
M3 - Journal article
AN - SCOPUS:85146252491
SN - 0278-0070
VL - 42
SP - 3067
EP - 3077
JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IS - 9
ER -