Explicit gate delay model for timing evaluation

Keyphrases

• Timing Analysis 100%
• Gate Delay 100%
• Drive Sources 100%
• Delay Model 100%
• Gate-level Models 100%
• High Performance 50%
• Conventional Techniques 50%
• Effective Capacitance 50%
• Downscaling 50%
• Modeling Techniques 50%
• Optimization Procedure 50%
• Design Improvement 50%
• Performance Optimization 50%
• Piecewise Linear Function 50%
• Voltage Source 50%
• Size Scaling 50%
• VLSI Design 50%
• Resistor Model 50%
• Deep Submicron Technology 50%
• Linear Output 50%
• Second-order Circuit 50%
• Synthesis Optimization 50%
• Gate Characteristics 50%
• Iterative Computation 50%
• Switch Region 50%
• Driving Resistance 50%
• Operating Frequency 50%
• Delay Evaluation 50%
• Two-pole 50%

Engineering

• Modeling Work 100%
• Optimisation Procedure 50%
• Interconnects 50%
• Linear Function 50%
• Operating Frequency 50%
• Feature Size 50%
• Voltage Source 50%
• Base Model 50%
• Conventional Technique 50%

Computer Science

• Timing Analysis 100%
• Performance Optimization 50%
• Piecewise Linear 50%
• Linear Function 50%
• Operating Frequency 50%