Enhancing ASIC HLS Design Optimization via Knowledge Transfer from FPGA HLS Models

This paper investigates the knowledge transfer from FPGA high-level synthesis (HLS) to ASIC HLS to overcome the data scarcity and high cost of building ASIC HLS performance models from scratch. We propose a transfer approach to adapt an FPGA HLS performance prediction model for ASIC HLS, motivated by the shared underlying principles and optimization goals between the two tasks. The proposed model disentangles the hidden features into separate pathways for shared and task-specific knowledge. To enhance transferability, we employ adversarial training and low-rank layers to encourage higher reliance on these generalizable features over those specific to FPGAs. Additionally, we refine the input feature representation to capture more precise design characteristics and introduce a rule-based pruning technique for efficient design space exploration (DSE). The synergy of these techniques leads to a 63.2% improvement in performance prediction and a 52.0% enhancement in DSE compared to a baseline trained from scratch. Our methodology demonstrates that transferred knowledge is beneficial and provides a systematic approach to leverage it, significantly advancing prediction and DSE for ASIC HLS.