Enhanced spacer-is-dielectric (SID) decomposition flow with model-based verification

Yuelin Du; Hua Song; James Shiely; Martin D.F. Wong

doi:10.1117/12.2011029

Enhanced spacer-is-dielectric (SID) decomposition flow with model-based verification

Yuelin Du, Hua Song, James Shiely, Martin D.F. Wong

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Research output: Chapter in book/report/conference proceeding › Conference proceeding › peer-review

5 Citations (Scopus)

Abstract

Self-aligned double patterning (SADP) lithography is a leading candidate for 14nm node lower-metal layer fabrication. Besides the intrinsic overlay-tolerance capability, the accurate spacer width and uniformity control enables such technology to fabricate very narrow and dense patterns. Spacer-is-dielectric (SID) is the most popular flavor of SADP with higher flexibility in design. In the SID process, due to uniform spacer deposition, the spacer shape gets rounded at convex mandrel corners, and disregarding the corner rounding issue during SID decomposition may result in severe residue artifacts on device patterns. Previously, SADP decomposition was merely verified by Boolean operations on the decomposed layers, where the residue artifacts are not even identifiable. This paper proposes a model-based verification method for SID decomposition to identify the artifacts caused by spacer corner rounding. Then targeting residue artifact removal, an enhanced SID decomposition flow is introduced. Simulation results show that residue artifacts are removed effectively through the enhanced SID decomposition strategy.

Original language	English
Title of host publication	Design for Manufacturability through Design-Process Integration VII
Editors	Mark E. Mason, John L. Sturtevant
Publisher	SPIE
ISBN (Print)	9780819494665
DOIs	https://doi.org/10.1117/12.2011029
Publication status	Published - Feb 2013
Event	SPIE Conference on Design for Manufacturability through Design-Process Integration VII, DfM-DPI 2013 - San Jose, United States Duration: 27 Feb 2013 → 28 Feb 2013 https://www.spiedigitallibrary.org/conference-proceedings-of-spie/8684.toc#FrontMatterVolume8684

Publication series

Name	Proceedings of SPIE - The International Society for Optical Engineering
Volume	8684
ISSN (Print)	0277-786X

Conference

Conference	SPIE Conference on Design for Manufacturability through Design-Process Integration VII, DfM-DPI 2013
Country/Territory	United States
City	San Jose
Period	27/02/13 → 28/02/13
Internet address	https://www.spiedigitallibrary.org/conference-proceedings-of-spie/8684.toc#FrontMatterVolume8684

Scopus Subject Areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Computer Science Applications
Applied Mathematics
Electrical and Electronic Engineering

User-Defined Keywords

Model-Based verification
Residue artifact removal
SID decomposition

Access to Document

10.1117/12.2011029

Cite this

Du, Y., Song, H., Shiely, J., & Wong, M. D. F. (2013). Enhanced spacer-is-dielectric (SID) decomposition flow with model-based verification. In M. E. Mason, & J. L. Sturtevant (Eds.), Design for Manufacturability through Design-Process Integration VII Article 86840D (Proceedings of SPIE - The International Society for Optical Engineering; Vol. 8684). SPIE. https://doi.org/10.1117/12.2011029

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abstract = "Self-aligned double patterning (SADP) lithography is a leading candidate for 14nm node lower-metal layer fabrication. Besides the intrinsic overlay-tolerance capability, the accurate spacer width and uniformity control enables such technology to fabricate very narrow and dense patterns. Spacer-is-dielectric (SID) is the most popular flavor of SADP with higher flexibility in design. In the SID process, due to uniform spacer deposition, the spacer shape gets rounded at convex mandrel corners, and disregarding the corner rounding issue during SID decomposition may result in severe residue artifacts on device patterns. Previously, SADP decomposition was merely verified by Boolean operations on the decomposed layers, where the residue artifacts are not even identifiable. This paper proposes a model-based verification method for SID decomposition to identify the artifacts caused by spacer corner rounding. Then targeting residue artifact removal, an enhanced SID decomposition flow is introduced. Simulation results show that residue artifacts are removed effectively through the enhanced SID decomposition strategy.",

keywords = "Model-Based verification, Residue artifact removal, SID decomposition",

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Du, Y, Song, H, Shiely, J & Wong, MDF 2013, Enhanced spacer-is-dielectric (SID) decomposition flow with model-based verification. in ME Mason & JL Sturtevant (eds), Design for Manufacturability through Design-Process Integration VII., 86840D, Proceedings of SPIE - The International Society for Optical Engineering, vol. 8684, SPIE, SPIE Conference on Design for Manufacturability through Design-Process Integration VII, DfM-DPI 2013, San Jose, California, United States, 27/02/13. https://doi.org/10.1117/12.2011029

Enhanced spacer-is-dielectric (SID) decomposition flow with model-based verification. / Du, Yuelin; Song, Hua; Shiely, James et al.
Design for Manufacturability through Design-Process Integration VII. ed. / Mark E. Mason; John L. Sturtevant . SPIE, 2013. 86840D (Proceedings of SPIE - The International Society for Optical Engineering; Vol. 8684).

Research output: Chapter in book/report/conference proceeding › Conference proceeding › peer-review

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N2 - Self-aligned double patterning (SADP) lithography is a leading candidate for 14nm node lower-metal layer fabrication. Besides the intrinsic overlay-tolerance capability, the accurate spacer width and uniformity control enables such technology to fabricate very narrow and dense patterns. Spacer-is-dielectric (SID) is the most popular flavor of SADP with higher flexibility in design. In the SID process, due to uniform spacer deposition, the spacer shape gets rounded at convex mandrel corners, and disregarding the corner rounding issue during SID decomposition may result in severe residue artifacts on device patterns. Previously, SADP decomposition was merely verified by Boolean operations on the decomposed layers, where the residue artifacts are not even identifiable. This paper proposes a model-based verification method for SID decomposition to identify the artifacts caused by spacer corner rounding. Then targeting residue artifact removal, an enhanced SID decomposition flow is introduced. Simulation results show that residue artifacts are removed effectively through the enhanced SID decomposition strategy.

AB - Self-aligned double patterning (SADP) lithography is a leading candidate for 14nm node lower-metal layer fabrication. Besides the intrinsic overlay-tolerance capability, the accurate spacer width and uniformity control enables such technology to fabricate very narrow and dense patterns. Spacer-is-dielectric (SID) is the most popular flavor of SADP with higher flexibility in design. In the SID process, due to uniform spacer deposition, the spacer shape gets rounded at convex mandrel corners, and disregarding the corner rounding issue during SID decomposition may result in severe residue artifacts on device patterns. Previously, SADP decomposition was merely verified by Boolean operations on the decomposed layers, where the residue artifacts are not even identifiable. This paper proposes a model-based verification method for SID decomposition to identify the artifacts caused by spacer corner rounding. Then targeting residue artifact removal, an enhanced SID decomposition flow is introduced. Simulation results show that residue artifacts are removed effectively through the enhanced SID decomposition strategy.

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Enhanced spacer-is-dielectric (SID) decomposition flow with model-based verification

Abstract

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User-Defined Keywords

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