Enhanced bottom-up algorithm for floorplan design

Thomas R. Mueller, D. F. Wong, C. L. Liu

Research output: Chapter in book/report/conference proceedingConference proceedingpeer-review

4 Citations (Scopus)


A fast algorithm for the design of floorplans is described. The algorithm can be used to carry out the complete design of a floorplan or to improve an existing floorplan. It is based on an enhanced bottom-up iterative improvement technique and can obtain good solutions with an increase in speed of approximately two orders of magnitude over an algorithm using the method of simulated annealing.

Original languageEnglish
Title of host publicationIEEE International Conference on Computer-Aided Design, ICCAD 1987: Digest of Technical Papers
Number of pages4
ISBN (Print)0818608145
Publication statusPublished - Nov 1987
EventIEEE International Conference on Computer-Aided Design, ICCAD 1987 - Santa Clara, United States
Duration: 9 Nov 198712 Nov 1987

Publication series

NameIEEE International Conference on Computer-Aided Design. Digest of Technical Papers


ConferenceIEEE International Conference on Computer-Aided Design, ICCAD 1987
Country/TerritoryUnited States
CitySanta Clara

Scopus Subject Areas

  • Engineering(all)


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