Efficient simulation-based optimization of power grid with on-chip voltage regulator

Ting Yu; Martin. D. F. Wong

doi:10.1109/ASPDAC.2014.6742946

Efficient simulation-based optimization of power grid with on-chip voltage regulator

Ting Yu, Martin. D. F. Wong

Office of the Provost

Research output: Chapter in book/report/conference proceeding › Conference proceeding › peer-review

4 Citations (Scopus)

Abstract

IR-drop values of power grid can be reduced through inserting on-chip low-dropout voltage regulators (LDO). In this paper, we explore the optimization of LDOs to meet the IR-drop constraint, where the maximum IR-drop value is less than 10% of power supply. With Cholesky direct solver and SPICE, we propose a method to simulate power grid with LDOs. Based on the simulation method, we develop an efficient flow to optimize the number and locations of the LDOs. Effectiveness of the proposed method is verified by the experimental results. To the best of our knowledge, this is the first work optimizing the number and locations of LDOs to meet the IR-drop constraint.

Original language	English
Title of host publication	2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC)
Publisher	IEEE
Pages	531-536
Number of pages	6
ISBN (Electronic)	9781479928163
DOIs	https://doi.org/10.1109/ASPDAC.2014.6742946
Publication status	Published - Jan 2014
Event	19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014 - , Singapore Duration: 20 Jan 2014 → 23 Jan 2014 https://ieeexplore.ieee.org/xpl/conhome/6736726/proceeding (Link to conference proceedings)

Publication series

Name	Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)

Conference

Conference	19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014
Country/Territory	Singapore
Period	20/01/14 → 23/01/14
Internet address	https://ieeexplore.ieee.org/xpl/conhome/6736726/proceeding (Link to conference proceedings)

Access to Document

10.1109/ASPDAC.2014.6742946

Cite this

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title = "Efficient simulation-based optimization of power grid with on-chip voltage regulator",

abstract = "IR-drop values of power grid can be reduced through inserting on-chip low-dropout voltage regulators (LDO). In this paper, we explore the optimization of LDOs to meet the IR-drop constraint, where the maximum IR-drop value is less than 10% of power supply. With Cholesky direct solver and SPICE, we propose a method to simulate power grid with LDOs. Based on the simulation method, we develop an efficient flow to optimize the number and locations of the LDOs. Effectiveness of the proposed method is verified by the experimental results. To the best of our knowledge, this is the first work optimizing the number and locations of LDOs to meet the IR-drop constraint.",

author = "Ting Yu and Wong, {Martin. D. F.}",

note = "Publisher Copyright: {\textcopyright} 2014, IEEE; 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014 ; Conference date: 20-01-2014 Through 23-01-2014",

year = "2014",

month = jan,

doi = "10.1109/ASPDAC.2014.6742946",

language = "English",

series = "Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)",

publisher = "IEEE",

pages = "531--536",

booktitle = "2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC)",

address = "United States",

url = "https://ieeexplore.ieee.org/xpl/conhome/6736726/proceeding",

}

Yu, T & Wong, MDF 2014, Efficient simulation-based optimization of power grid with on-chip voltage regulator. in 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC)., 6742946, Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), IEEE, pp. 531-536, 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014, Singapore, 20/01/14. https://doi.org/10.1109/ASPDAC.2014.6742946

Efficient simulation-based optimization of power grid with on-chip voltage regulator. / Yu, Ting; Wong, Martin. D. F.
2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC). IEEE, 2014. p. 531-536 6742946 (Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)).

Research output: Chapter in book/report/conference proceeding › Conference proceeding › peer-review

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AU - Wong, Martin. D. F.

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N2 - IR-drop values of power grid can be reduced through inserting on-chip low-dropout voltage regulators (LDO). In this paper, we explore the optimization of LDOs to meet the IR-drop constraint, where the maximum IR-drop value is less than 10% of power supply. With Cholesky direct solver and SPICE, we propose a method to simulate power grid with LDOs. Based on the simulation method, we develop an efficient flow to optimize the number and locations of the LDOs. Effectiveness of the proposed method is verified by the experimental results. To the best of our knowledge, this is the first work optimizing the number and locations of LDOs to meet the IR-drop constraint.

AB - IR-drop values of power grid can be reduced through inserting on-chip low-dropout voltage regulators (LDO). In this paper, we explore the optimization of LDOs to meet the IR-drop constraint, where the maximum IR-drop value is less than 10% of power supply. With Cholesky direct solver and SPICE, we propose a method to simulate power grid with LDOs. Based on the simulation method, we develop an efficient flow to optimize the number and locations of the LDOs. Effectiveness of the proposed method is verified by the experimental results. To the best of our knowledge, this is the first work optimizing the number and locations of LDOs to meet the IR-drop constraint.

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DO - 10.1109/ASPDAC.2014.6742946

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T3 - Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)

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BT - 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC)

PB - IEEE

T2 - 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014

Y2 - 20 January 2014 through 23 January 2014

ER -

Efficient simulation-based optimization of power grid with on-chip voltage regulator

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