Efficient ASIP design for configurable processors with fine-grained resource sharing

Quang Dinh; Deming Chen; Martin D. F. Wong

doi:10.1145/1344671.1344687

Efficient ASIP design for configurable processors with fine-grained resource sharing

Quang Dinh, Deming Chen, Martin D. F. Wong

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Research output: Chapter in book/report/conference proceeding › Conference proceeding › peer-review

13 Citations (Scopus)

Abstract

Application-Specific Instruction-set Processors (ASIP) can improve execution speed by using custom instructions. Several ASIP design automation flows have been proposed recently. In this paper, we investigate two techniques to improve these flows, so that ASIP can be efficiently applied to simple computer architectures in embedded applications. Firstly, we efficiently generate custom instructions with multi-cycle IO (which allows multi-outputs), thus removing the constraint imposed by the ports of the register file. Secondly, we allow identical portions of different custom instructions to be shared, thus allowing more custom instructions under the same area constraint. To handle the greatly increased exploration space, we propose several heuristics to keep the problem tractable. Experimental results show that we can achieve 3x speedup in some cases.

Original language	English
Title of host publication	FPGA '08
Subtitle of host publication	Proceedings of the 16th International Symposium on Field-Programmable Gate Arrays
Publisher	Association for Computing Machinery (ACM)
Pages	99-106
Number of pages	8
ISBN (Print)	9781595939340
DOIs	https://doi.org/10.1145/1344671.1344687
Publication status	Published - 25 Feb 2008
Event	16th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2008 - Monterey, United States Duration: 24 Feb 2008 → 26 Feb 2008 https://www.isfpga.org/past/fpga2008/ (Conference website) https://www.isfpga.org/past/fpga2008/FPGA2008program.html (Conference programme) https://dl.acm.org/doi/proceedings/10.1145/1344671 (Conference proceedings)

Publication series

Name	Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA

Symposium

Symposium	16th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2008
Country/Territory	United States
City	Monterey
Period	24/02/08 → 26/02/08
Internet address	https://www.isfpga.org/past/fpga2008/ (Conference website) https://www.isfpga.org/past/fpga2008/FPGA2008program.html (Conference programme) https://dl.acm.org/doi/proceedings/10.1145/1344671 (Conference proceedings)

Scopus Subject Areas

General Computer Science

User-Defined Keywords

Algorithms
Performance
Design
Experimentation

Access to Document

10.1145/1344671.1344687

Cite this

Dinh, Q., Chen, D., & Wong, M. D. F. (2008). Efficient ASIP design for configurable processors with fine-grained resource sharing. In FPGA '08: Proceedings of the 16th International Symposium on Field-Programmable Gate Arrays (pp. 99-106). (Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA). Association for Computing Machinery (ACM). https://doi.org/10.1145/1344671.1344687

Dinh, Quang ; Chen, Deming ; Wong, Martin D. F. / Efficient ASIP design for configurable processors with fine-grained resource sharing. FPGA '08: Proceedings of the 16th International Symposium on Field-Programmable Gate Arrays. Association for Computing Machinery (ACM), 2008. pp. 99-106 (Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA).

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abstract = "Application-Specific Instruction-set Processors (ASIP) can improve execution speed by using custom instructions. Several ASIP design automation flows have been proposed recently. In this paper, we investigate two techniques to improve these flows, so that ASIP can be efficiently applied to simple computer architectures in embedded applications. Firstly, we efficiently generate custom instructions with multi-cycle IO (which allows multi-outputs), thus removing the constraint imposed by the ports of the register file. Secondly, we allow identical portions of different custom instructions to be shared, thus allowing more custom instructions under the same area constraint. To handle the greatly increased exploration space, we propose several heuristics to keep the problem tractable. Experimental results show that we can achieve 3x speedup in some cases.",

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Dinh, Q, Chen, D & Wong, MDF 2008, Efficient ASIP design for configurable processors with fine-grained resource sharing. in FPGA '08: Proceedings of the 16th International Symposium on Field-Programmable Gate Arrays. Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA, Association for Computing Machinery (ACM), pp. 99-106, 16th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2008, Monterey, California, United States, 24/02/08. https://doi.org/10.1145/1344671.1344687

Efficient ASIP design for configurable processors with fine-grained resource sharing. / Dinh, Quang; Chen, Deming; Wong, Martin D. F.
FPGA '08: Proceedings of the 16th International Symposium on Field-Programmable Gate Arrays. Association for Computing Machinery (ACM), 2008. p. 99-106 (Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA).

Research output: Chapter in book/report/conference proceeding › Conference proceeding › peer-review

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Dinh Q, Chen D, Wong MDF. Efficient ASIP design for configurable processors with fine-grained resource sharing. In FPGA '08: Proceedings of the 16th International Symposium on Field-Programmable Gate Arrays. Association for Computing Machinery (ACM). 2008. p. 99-106. (Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA). doi: 10.1145/1344671.1344687

Efficient ASIP design for configurable processors with fine-grained resource sharing

Abstract

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Symposium

Scopus Subject Areas

User-Defined Keywords

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