Edge-map: optimal performance driven technology mapping for iterative LUT based FPGA designs

Honghua Yang; D. F. Wong

doi:10.1109/ICCAD.1994.629758

Edge-map: optimal performance driven technology mapping for iterative LUT based FPGA designs

Honghua Yang, D. F. Wong

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Research output: Chapter in book/report/conference proceeding › Chapter › peer-review

24 Citations (Scopus)

Abstract

An efficient technology mapping algorithm that achieves probably optimal delay in the technology mapped circuit using the general delay model is presented. The algorithm is a non-trivial generalization of FlowMap. A key problem in the algorithm is to compute a K-feasible network cut such that the circuit delay on every cut edge is upper-bounded by a specific value. The algorithm is implemented in a lookup-table (LUT) based FPGA technology mapping package called Edge-Map, and Edge-Map is tested on a set of benchmark circuits.

Original language	English
Title of host publication	1994 IEEE/ACM International Conference On Computer-aided Design, ICCAD 1994
Publisher	IEEE
Pages	150-155
Number of pages	6
ISBN (Print)	0818664177, 0818630108
DOIs	https://doi.org/10.1109/ICCAD.1994.629758
Publication status	Published - Nov 1994
Event	1994 IEEE/ACM International Conference on Computer-aided Design, ICCAD 1994 - San Jose, United States Duration: 6 Nov 1994 → 10 Nov 1994 https://ieeexplore.ieee.org/xpl/conhome/4983/proceeding (Link to conference proceedings)

Publication series

Name	Proceedings of IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Conference

Conference	1994 IEEE/ACM International Conference on Computer-aided Design, ICCAD 1994
Country/Territory	United States
City	San Jose
Period	6/11/94 → 10/11/94
Internet address	https://ieeexplore.ieee.org/xpl/conhome/4983/proceeding (Link to conference proceedings)

Access to Document

10.1109/ICCAD.1994.629758

Cite this

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title = "Edge-map: optimal performance driven technology mapping for iterative LUT based FPGA designs",

abstract = "An efficient technology mapping algorithm that achieves probably optimal delay in the technology mapped circuit using the general delay model is presented. The algorithm is a non-trivial generalization of FlowMap. A key problem in the algorithm is to compute a K-feasible network cut such that the circuit delay on every cut edge is upper-bounded by a specific value. The algorithm is implemented in a lookup-table (LUT) based FPGA technology mapping package called Edge-Map, and Edge-Map is tested on a set of benchmark circuits.",

author = "Honghua Yang and Wong, {D. F.}",

note = "Funding Information: This work was partially supported by the Texas Advanced Research Program under Grant No 003658459, by an Intel Foundation Graduate Fellowship, by a DAC Design Automation Scholarship, and by a grant from AT&T Bell Laboratories. Publisher Copyright: {\textcopyright} 1994 ACM ; 1994 IEEE/ACM International Conference on Computer-aided Design, ICCAD 1994 ; Conference date: 06-11-1994 Through 10-11-1994",

year = "1994",

month = nov,

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language = "English",

isbn = "0818664177",

series = "Proceedings of IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems",

publisher = "IEEE",

pages = "150--155",

booktitle = "1994 IEEE/ACM International Conference On Computer-aided Design, ICCAD 1994",

address = "United States",

url = "https://ieeexplore.ieee.org/xpl/conhome/4983/proceeding",

}

Yang, H & Wong, DF 1994, Edge-map: optimal performance driven technology mapping for iterative LUT based FPGA designs. in 1994 IEEE/ACM International Conference On Computer-aided Design, ICCAD 1994. Proceedings of IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE, pp. 150-155, 1994 IEEE/ACM International Conference on Computer-aided Design, ICCAD 1994, San Jose, California, United States, 6/11/94. https://doi.org/10.1109/ICCAD.1994.629758

Edge-map: optimal performance driven technology mapping for iterative LUT based FPGA designs. / Yang, Honghua; Wong, D. F.
1994 IEEE/ACM International Conference On Computer-aided Design, ICCAD 1994. IEEE, 1994. p. 150-155 (Proceedings of IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems).

Research output: Chapter in book/report/conference proceeding › Chapter › peer-review

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T1 - Edge-map

T2 - 1994 IEEE/ACM International Conference on Computer-aided Design, ICCAD 1994

AU - Yang, Honghua

AU - Wong, D. F.

N1 - Funding Information: This work was partially supported by the Texas Advanced Research Program under Grant No 003658459, by an Intel Foundation Graduate Fellowship, by a DAC Design Automation Scholarship, and by a grant from AT&T Bell Laboratories. Publisher Copyright: © 1994 ACM

PY - 1994/11

Y1 - 1994/11

N2 - An efficient technology mapping algorithm that achieves probably optimal delay in the technology mapped circuit using the general delay model is presented. The algorithm is a non-trivial generalization of FlowMap. A key problem in the algorithm is to compute a K-feasible network cut such that the circuit delay on every cut edge is upper-bounded by a specific value. The algorithm is implemented in a lookup-table (LUT) based FPGA technology mapping package called Edge-Map, and Edge-Map is tested on a set of benchmark circuits.

AB - An efficient technology mapping algorithm that achieves probably optimal delay in the technology mapped circuit using the general delay model is presented. The algorithm is a non-trivial generalization of FlowMap. A key problem in the algorithm is to compute a K-feasible network cut such that the circuit delay on every cut edge is upper-bounded by a specific value. The algorithm is implemented in a lookup-table (LUT) based FPGA technology mapping package called Edge-Map, and Edge-Map is tested on a set of benchmark circuits.

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DO - 10.1109/ICCAD.1994.629758

M3 - Chapter

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SN - 0818630108

T3 - Proceedings of IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

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EP - 155

BT - 1994 IEEE/ACM International Conference On Computer-aided Design, ICCAD 1994

PB - IEEE

Y2 - 6 November 1994 through 10 November 1994

ER -

Edge-map: optimal performance driven technology mapping for iterative LUT based FPGA designs

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