TY - GEN
T1 - EDGE: DBMS-Empowered Boolean Decomposition for GIG Synthesis
AU - Tang, Ruofei
AU - Zhu, Xuliang
AU - Zhang, Xinyi
AU - Chen, Lei
AU - Li, Xing
AU - Yuan, Mingxuan
AU - Xu, Jianliang
N1 - This work is partially supported by the Hong Kong Research Grants Council and Guangdong Basic and Applied Basic Research Foundation (Project No. 2023B1515130002). Lei Chen is the corresponding author.
Publisher Copyright:
© 2025 IEEE.
PY - 2025/6/22
Y1 - 2025/6/22
N2 - Boolean decomposition is a powerful technique in logic synthesis that breaks down Boolean functions into simpler components. Decomposition-based logic synthesis yields high-quality results and is particularly effective when combined with small-window optimization methods in Gate-Inverter Graphs (GIG). However, the efficiency limitations of current methods have constrained their applicability in handling large and complex logic. To address this challenge, we propose a novel framework, called EDGE, which leverages modern database techniques to accelerate Boolean decomposition, thereby achieving improved synthesis results while maintaining high efficiency. Experimental results demonstrate a runtime speedup of up to 21 × and an overall reduction in node count of at least 15% compared to state-of-the-art synthesis methods.
AB - Boolean decomposition is a powerful technique in logic synthesis that breaks down Boolean functions into simpler components. Decomposition-based logic synthesis yields high-quality results and is particularly effective when combined with small-window optimization methods in Gate-Inverter Graphs (GIG). However, the efficiency limitations of current methods have constrained their applicability in handling large and complex logic. To address this challenge, we propose a novel framework, called EDGE, which leverages modern database techniques to accelerate Boolean decomposition, thereby achieving improved synthesis results while maintaining high efficiency. Experimental results demonstrate a runtime speedup of up to 21 × and an overall reduction in node count of at least 15% compared to state-of-the-art synthesis methods.
UR - https://www.scopus.com/pages/publications/105017583524
U2 - 10.1109/DAC63849.2025.11133306
DO - 10.1109/DAC63849.2025.11133306
M3 - Conference proceeding
AN - SCOPUS:105017583524
SN - 9798331503055
T3 - Proceedings - Design Automation Conference
BT - 2025 62nd ACM/IEEE Design Automation Conference, DAC 2025
PB - IEEE
T2 - 62nd ACM/IEEE Design Automation Conference, DAC 2025
Y2 - 22 June 2025 through 25 June 2025
ER -
