Abstract
In modern VLSI manufacturing processes, dummy fills are widely used to adjust local metal density in order to improve layout uniformity and yield optimization. However, the introduction of a large amount of dummy features also affects wire electrical properties. In this paper, we propose the first Coupling constrained Dummy Fill (CDF) analysis algorithm which identifies feasible locations for dummy fills such that the fill induced coupling capacitance can be bounded within the given coupling threshold of each wire segment. The algorithm also makes efforts to maximize ground dummy fills, which are more robust and predictable. The output of the algorithm can be treated as the upper bound for dummy fill insertion, and it can be easily adopted in density models to guide dummy fill insertion without disturbing the existing design.
Original language | English |
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Title of host publication | ISPD '07 |
Subtitle of host publication | Proceedings of the 2007 International Symposium on Physical Design |
Pages | 3-10 |
Number of pages | 8 |
DOIs | |
Publication status | Published - 18 Mar 2007 |
Event | 16th International Symposium on Physical Design, ISPD 2007 - Austin , United States Duration: 18 Mar 2007 → 21 Mar 2007 https://dl.acm.org/doi/proceedings/10.1145/1231996 (Conference proceedings) |
Publication series
Name | Proceedings of the International Symposium on Physical Design, ISPD |
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Symposium
Symposium | 16th International Symposium on Physical Design, ISPD 2007 |
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Country/Territory | United States |
City | Austin |
Period | 18/03/07 → 21/03/07 |
Internet address |
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Scopus Subject Areas
- Electrical and Electronic Engineering
User-Defined Keywords
- dummy fills
- coupling
- CMP