Delay minimal decomposition of multiplexers in technology mapping

Shashidhar Thakur, D.F. Wong, Shankar Krishnamoorthy

Research output: Chapter in book/report/conference proceedingChapterpeer-review

13 Citations (Scopus)

Abstract

Technology mapping requires the unmapped logic network to be represented in terms of base functions, usually two-input NORs and inverters. Technology decomposition is the step that transforms arbitrary networks to this form. Typically, such decomposition schemes ignore the fact that certain circuit elements can be mapped more efficiently by treating them separately during decomposition. Multiplexers are one such category of circuit elements. They appear very naturally in circuits, in the form of datapath elements and as a result of synthesis of CASE statements in HDL specifications of control logic. Mapping them using multiplexers in technology libraries has many advantages. In this paper, we give an algorithm for optimally decomposing multiplexers, so as to minimize the delay of the network, and demonstrate its effectiveness in improving the quality of mapped circuits.

Original languageEnglish
Title of host publication33rd ACM/IEEE Design Automation Conference - Proceedings 1996
PublisherAssociation for Computing Machinery (ACM)
Pages254-257
Number of pages4
ISBN (Print)9780897917797, 0780332946
DOIs
Publication statusPublished - Jun 1996
Event33rd ACM/IEEE Design Automation Conference, DAC 1996 - Las Vegas, United States
Duration: 3 Jun 19967 Jun 1996
https://dl.acm.org/doi/proceedings/10.1145/240518 (Link to conference proceedings)
https://ieeexplore.ieee.org/xpl/conhome/3826/proceeding

Publication series

NameACM/IEEE Design Automation Conference - Proceedings
ISSN (Print)0738-100X

Conference

Conference33rd ACM/IEEE Design Automation Conference, DAC 1996
Country/TerritoryUnited States
CityLas Vegas
Period3/06/967/06/96
Internet address

Scopus Subject Areas

  • Hardware and Architecture
  • Control and Systems Engineering

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