DDBDD: Delay-driven BPD synthesis for FPGAs

Keyphrases

• Binary Decision Diagram 100%
• Performance Gain 42%
• Field Programmable Gate Arrays 42%
• Area Overhead 42%
• Performance Optimization 28%
• Linear Expansion 28%
• Array Performance 28%
• Dynamic Programming Algorithm 14%
• Size Reduction 14%
• Optimization Space 14%
• Initial Design 14%
• Logic Synthesis 14%
• Synthesis Tool 14%
• Mapper 14%
• Target Field 14%
• Delay Reduction 14%
• Array Synthesis 14%

Engineering

• Field Programmable Gate Array 100%
• Area Overhead 75%
• Linear Expansion 50%
• Experimental Result 25%
• Nodes 25%
• Size Reduction 25%
• Dynamic Programming 25%
• Logic Synthesis 25%
• Initial Design 25%

Computer Science

• Field Programmable Gate Array 100%
• binary decision diagram 100%
• Performance Gain 42%
• Performance Optimization 28%
• Experimental Result 14%
• Dynamic Programming Algorithm 14%
• Logic Synthesis 14%
• Synthesis Tool 14%
• Optimization Space 14%