DDBDD: delay-driven BDD synthesis for FPGAs

Keyphrases

• Performance Optimization 100%
• Linear Expansion 100%
• Synthetic Approaches 50%
• Graph-based 50%
• Dynamic Programming Algorithm 50%
• Size Reduction 50%
• Optimization Space 50%
• Binary Choice 50%
• Initial Design 50%
• Logic Synthesis 50%
• Synthesis Tool 50%
• Area Overhead 50%
• Delay Reduction 50%
• FPGA Synthesis 50%
• Network Depth 50%
• Decision Diagrams 50%

Engineering

• Field Programmable Gate Array 100%
• Linear Expansion 50%
• Experimental Result 25%
• Nodes 25%
• Size Reduction 25%
• Dynamic Programming 25%
• Logic Synthesis 25%
• Area Overhead 25%
• Initial Design 25%

Computer Science

• Field Programmable Gate Array 100%
• Performance Optimization 50%
• Experimental Result 25%
• Binary Decision 25%
• Dynamic Programming Algorithm 25%
• Logic Synthesis 25%
• Synthesis Tool 25%
• Optimization Space 25%