CPP: A Multi-Level Circuit Partitioning Predictor for Hardware Verification Systems

Xinshi Zang; Lei Chen; Xing Li; Wilson W.K. Thong; Weihua Sheng; Evangeline F.Y. Young; Martin D.F. Wong

doi:10.1145/3583781.3590289

CPP: A Multi-Level Circuit Partitioning Predictor for Hardware Verification Systems

Xinshi Zang, Lei Chen, Xing Li, Wilson W.K. Thong, Weihua Sheng, Evangeline F.Y. Young, Martin D.F. Wong

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Research output: Chapter in book/report/conference proceeding › Conference proceeding › peer-review

Abstract

Circuit partitioning is a critical step in hardware-assisted functional verification that involves splitting a circuit into multiple partitions and assigning them to specific hardware. However, partitioning a large circuit can require considerable computation resources and time, especially when complex hardware constraints are involved. Moreover, the path delay after partitioning can have a significant impact on verification efficiency, making early path delay prediction crucial for refining the circuit effectively. In this work, we propose a novel circuit partitioning predictor, named CPP, to rapidly and accurately predict the path delay after partitioning. To achieve this, we use circuit coarsening to develop a multi-level path representation and employ a convolutional neural network (CNN) that can capture both local and global path structures for delay prediction. Through extensive experiments on large industrial circuits, we demonstrate the superiority of our prediction framework.

Original language	English
Title of host publication	GLSVLSI 2023 - Proceedings of the Great Lakes Symposium on VLSI 2023
Publisher	Association for Computing Machinery (ACM)
Pages	357-361
Number of pages	5
ISBN (Print)	9798400701252
DOIs	https://doi.org/10.1145/3583781.3590289
Publication status	Published - 5 Jun 2023
Event	33rd Great Lakes Symposium on VLSI, GLSVLSI 2023 - Knoxville, United States Duration: 5 Jun 2023 → 7 Jun 2023 https://dl.acm.org/doi/proceedings/10.1145/3583781

Publication series

Name	Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Conference

Conference	33rd Great Lakes Symposium on VLSI, GLSVLSI 2023
Country/Territory	United States
City	Knoxville
Period	5/06/23 → 7/06/23
Internet address	https://dl.acm.org/doi/proceedings/10.1145/3583781

Scopus Subject Areas

General Engineering

User-Defined Keywords

circuit verification
partitioning
synthesis

Access to Document

10.1145/3583781.3590289

Cite this

Zang, X., Chen, L., Li, X., Thong, W. W. K., Sheng, W., Young, E. F. Y., & Wong, M. D. F. (2023). CPP: A Multi-Level Circuit Partitioning Predictor for Hardware Verification Systems. In GLSVLSI 2023 - Proceedings of the Great Lakes Symposium on VLSI 2023 (pp. 357-361). (Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI). Association for Computing Machinery (ACM). https://doi.org/10.1145/3583781.3590289

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title = "CPP: A Multi-Level Circuit Partitioning Predictor for Hardware Verification Systems",

abstract = "Circuit partitioning is a critical step in hardware-assisted functional verification that involves splitting a circuit into multiple partitions and assigning them to specific hardware. However, partitioning a large circuit can require considerable computation resources and time, especially when complex hardware constraints are involved. Moreover, the path delay after partitioning can have a significant impact on verification efficiency, making early path delay prediction crucial for refining the circuit effectively. In this work, we propose a novel circuit partitioning predictor, named CPP, to rapidly and accurately predict the path delay after partitioning. To achieve this, we use circuit coarsening to develop a multi-level path representation and employ a convolutional neural network (CNN) that can capture both local and global path structures for delay prediction. Through extensive experiments on large industrial circuits, we demonstrate the superiority of our prediction framework.",

keywords = "circuit verification, partitioning, synthesis",

author = "Xinshi Zang and Lei Chen and Xing Li and Thong, {Wilson W.K.} and Weihua Sheng and Young, {Evangeline F.Y.} and Wong, {Martin D.F.}",

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Zang, X, Chen, L, Li, X, Thong, WWK, Sheng, W, Young, EFY & Wong, MDF 2023, CPP: A Multi-Level Circuit Partitioning Predictor for Hardware Verification Systems. in GLSVLSI 2023 - Proceedings of the Great Lakes Symposium on VLSI 2023. Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI, Association for Computing Machinery (ACM), pp. 357-361, 33rd Great Lakes Symposium on VLSI, GLSVLSI 2023, Knoxville, United States, 5/06/23. https://doi.org/10.1145/3583781.3590289

CPP: A Multi-Level Circuit Partitioning Predictor for Hardware Verification Systems. / Zang, Xinshi; Chen, Lei; Li, Xing et al.
GLSVLSI 2023 - Proceedings of the Great Lakes Symposium on VLSI 2023. Association for Computing Machinery (ACM), 2023. p. 357-361 (Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI).

Research output: Chapter in book/report/conference proceeding › Conference proceeding › peer-review

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AB - Circuit partitioning is a critical step in hardware-assisted functional verification that involves splitting a circuit into multiple partitions and assigning them to specific hardware. However, partitioning a large circuit can require considerable computation resources and time, especially when complex hardware constraints are involved. Moreover, the path delay after partitioning can have a significant impact on verification efficiency, making early path delay prediction crucial for refining the circuit effectively. In this work, we propose a novel circuit partitioning predictor, named CPP, to rapidly and accurately predict the path delay after partitioning. To achieve this, we use circuit coarsening to develop a multi-level path representation and employ a convolutional neural network (CNN) that can capture both local and global path structures for delay prediction. Through extensive experiments on large industrial circuits, we demonstrate the superiority of our prediction framework.

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Zang X, Chen L, Li X, Thong WWK, Sheng W, Young EFY et al. CPP: A Multi-Level Circuit Partitioning Predictor for Hardware Verification Systems. In GLSVLSI 2023 - Proceedings of the Great Lakes Symposium on VLSI 2023. Association for Computing Machinery (ACM). 2023. p. 357-361. (Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI). doi: 10.1145/3583781.3590289

CPP: A Multi-Level Circuit Partitioning Predictor for Hardware Verification Systems

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