Abstract
As integrated circuits manufacturing technology is advancing into 65nm and 45nm nodes, extensive resolution enhancement techniques (RET) are needed to correctly manufacture a chip design. The widely used RET called off-axis illumination (OAI) introduces forbidden pitches which lead to very complex design rules. It has been observed that imposing uniformity on layout designs can substantially improve printability under OAI. In this paper, two types of assist features for the metal layer are proposed to improve the uniformity, printable assist feature and segmented printable assist feature. They bring different costs on performance and manufacturing. Coupling and lithography costs from these assist features are discussed. Optimal insertion algorithm is proposed to use both types of dummy metals, considering trade-offs between coupling and lithography costs.
Original language | English |
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Title of host publication | Design for Manufacturability through Design-Process Integration |
Editors | Alfred K. K. Wong , Vivek K. Singh |
Publisher | SPIE |
ISBN (Print) | 0819466409, 9780819466402 |
DOIs | |
Publication status | Published - Mar 2007 |
Event | Design for Manufacturability through Design-Process Integration - San Jose, United States Duration: 28 Feb 2007 → 2 Mar 2007 https://www.spiedigitallibrary.org/conference-proceedings-of-spie/6521.toc |
Publication series
Name | Proceedings of SPIE - The International Society for Optical Engineering |
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Volume | 6521 |
ISSN (Print) | 0277-786X |
Conference
Conference | Design for Manufacturability through Design-Process Integration |
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Country/Territory | United States |
City | San Jose |
Period | 28/02/07 → 2/03/07 |
Internet address |
Scopus Subject Areas
- Electronic, Optical and Magnetic Materials
- Condensed Matter Physics
- Computer Science Applications
- Applied Mathematics
- Electrical and Electronic Engineering
User-Defined Keywords
- Assist feature
- Coupling capacitance
- Lithography cost
- RET
- SPAF