Concurrent Sign-off Timing Optimization via Deep Steiner Points Refinement

Siting Liu; Ziyi Wang; Fangzhou Liu; Yibo Lin; Bei Yu; Martin Wong

doi:10.1109/DAC56929.2023.10247794

Concurrent Sign-off Timing Optimization via Deep Steiner Points Refinement

Siting Liu, Ziyi Wang, Fangzhou Liu, Yibo Lin, Bei Yu, Martin Wong

Office of the Provost

Research output: Chapter in book/report/conference proceeding › Conference proceeding › peer-review

3 Citations (Scopus)

Abstract

Timing closure is crucial across the circuit design flow. Since obtaining sign-off performance needs a time-consuming routing flow, all the previous early-stage timing optimization works only focus on improving early timing metrics, e.g., rough timing estimation using linear RC model or pre-routing path-length. However, there is no consistency guarantee between early-stage metrics and sign-off timing performance. To enable explicit early-stage optimization on the sign-off timing metrics, we propose a novel timing optimization framework, TSteiner. This paper demonstrates the ability of the learning framework to perform robust and efficient timing optimization in the early stage with comprehensive and convincing experimental results on real-world designs.

Original language	English
Title of host publication	60th ACM/IEEE Design Automation Conference - Proceedings 2023
Publisher	IEEE
Pages	1-6
Number of pages	6
ISBN (Electronic)	9798350323481
ISBN (Print)	9798350323498
DOIs	https://doi.org/10.1109/DAC56929.2023.10247794
Publication status	Published - 13 Jul 2023
Event	60th ACM/IEEE Design Automation Conference, DAC 2023 - Moscone West, San Francisco, United States Duration: 9 Jul 2023 → 13 Jul 2023 https://www.dac.com/ https://60dac.conference-program.com/ https://ieeexplore.ieee.org/xpl/conhome/10247654/proceeding

Publication series

Name	ACM/IEEE Design Automation Conference - Proceedings
Volume	2023-July
ISSN (Print)	0738-100X

Conference

Conference	60th ACM/IEEE Design Automation Conference, DAC 2023
Country/Territory	United States
City	San Francisco
Period	9/07/23 → 13/07/23
Internet address	https://www.dac.com/ https://60dac.conference-program.com/ https://ieeexplore.ieee.org/xpl/conhome/10247654/proceeding

Scopus Subject Areas

Electrical and Electronic Engineering
Control and Systems Engineering
Computer Science Applications
Modelling and Simulation

User-Defined Keywords

Estimation
Measurement
Pins
Routing
Runtime
Steiner trees
Timing

Access to Document

10.1109/DAC56929.2023.10247794

Cite this

@inproceedings{74a23b498d784959a8bdc980410a909d,

title = "Concurrent Sign-off Timing Optimization via Deep Steiner Points Refinement",

abstract = "Timing closure is crucial across the circuit design flow. Since obtaining sign-off performance needs a time-consuming routing flow, all the previous early-stage timing optimization works only focus on improving early timing metrics, e.g., rough timing estimation using linear RC model or pre-routing path-length. However, there is no consistency guarantee between early-stage metrics and sign-off timing performance. To enable explicit early-stage optimization on the sign-off timing metrics, we propose a novel timing optimization framework, TSteiner. This paper demonstrates the ability of the learning framework to perform robust and efficient timing optimization in the early stage with comprehensive and convincing experimental results on real-world designs.",

keywords = "Estimation, Measurement, Pins, Routing, Runtime, Steiner trees, Timing",

author = "Siting Liu and Ziyi Wang and Fangzhou Liu and Yibo Lin and Bei Yu and Martin Wong",

note = "Funding Information: This work is supported by The Research Grants Council of Hong Kong SAR (No. CUHK14209420) and The 111 Project (No. B18001). Publisher Copyright: {\textcopyright} 2023 IEEE.; 60th ACM/IEEE Design Automation Conference, DAC 2023 ; Conference date: 09-07-2023 Through 13-07-2023",

year = "2023",

month = jul,

day = "13",

doi = "10.1109/DAC56929.2023.10247794",

language = "English",

isbn = "9798350323498",

series = "ACM/IEEE Design Automation Conference - Proceedings",

publisher = "IEEE",

pages = "1--6",

booktitle = "60th ACM/IEEE Design Automation Conference - Proceedings 2023",

address = "United States",

url = "https://www.dac.com/, https://60dac.conference-program.com/, https://ieeexplore.ieee.org/xpl/conhome/10247654/proceeding",

}

Liu, S, Wang, Z, Liu, F, Lin, Y, Yu, B & Wong, M 2023, Concurrent Sign-off Timing Optimization via Deep Steiner Points Refinement. in 60th ACM/IEEE Design Automation Conference - Proceedings 2023. ACM/IEEE Design Automation Conference - Proceedings, vol. 2023-July, IEEE, pp. 1-6, 60th ACM/IEEE Design Automation Conference, DAC 2023, San Francisco, California, United States, 9/07/23. https://doi.org/10.1109/DAC56929.2023.10247794

Concurrent Sign-off Timing Optimization via Deep Steiner Points Refinement. / Liu, Siting; Wang, Ziyi; Liu, Fangzhou et al.
60th ACM/IEEE Design Automation Conference - Proceedings 2023. IEEE, 2023. p. 1-6 (ACM/IEEE Design Automation Conference - Proceedings; Vol. 2023-July).

Research output: Chapter in book/report/conference proceeding › Conference proceeding › peer-review

TY - GEN

T1 - Concurrent Sign-off Timing Optimization via Deep Steiner Points Refinement

AU - Liu, Siting

AU - Wang, Ziyi

AU - Liu, Fangzhou

AU - Lin, Yibo

AU - Yu, Bei

AU - Wong, Martin

PY - 2023/7/13

Y1 - 2023/7/13

N2 - Timing closure is crucial across the circuit design flow. Since obtaining sign-off performance needs a time-consuming routing flow, all the previous early-stage timing optimization works only focus on improving early timing metrics, e.g., rough timing estimation using linear RC model or pre-routing path-length. However, there is no consistency guarantee between early-stage metrics and sign-off timing performance. To enable explicit early-stage optimization on the sign-off timing metrics, we propose a novel timing optimization framework, TSteiner. This paper demonstrates the ability of the learning framework to perform robust and efficient timing optimization in the early stage with comprehensive and convincing experimental results on real-world designs.

AB - Timing closure is crucial across the circuit design flow. Since obtaining sign-off performance needs a time-consuming routing flow, all the previous early-stage timing optimization works only focus on improving early timing metrics, e.g., rough timing estimation using linear RC model or pre-routing path-length. However, there is no consistency guarantee between early-stage metrics and sign-off timing performance. To enable explicit early-stage optimization on the sign-off timing metrics, we propose a novel timing optimization framework, TSteiner. This paper demonstrates the ability of the learning framework to perform robust and efficient timing optimization in the early stage with comprehensive and convincing experimental results on real-world designs.

KW - Estimation

KW - Measurement

KW - Pins

KW - Routing

KW - Runtime

KW - Steiner trees

KW - Timing

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Concurrent Sign-off Timing Optimization via Deep Steiner Points Refinement

Abstract

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Scopus Subject Areas

User-Defined Keywords

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