Compacted channel routing with via placement restrictions

D. F. Wong; C. L. Liu

doi:10.1016/0167-9260(86)90011-8

Compacted channel routing with via placement restrictions

D. F. Wong^*, C. L. Liu

^*Corresponding author for this work

Office of the Provost

Research output: Contribution to journal › Journal article › peer-review

13 Citations (Scopus)

Abstract

We study in this paper the channel routing problem when there are restrictions on the placement of via holes. We show how to produce routing solutions that contain no horizontally adjacent vias and a close to minimum number of vertically and diagonally adjacent vias. Such solutions lead to compaction that will reduce total routing area.

Original language	English
Pages (from-to)	287-307
Number of pages	21
Journal	Integration, the VLSI Journal
Volume	4
Issue number	4
DOIs	https://doi.org/10.1016/0167-9260(86)90011-8
Publication status	Published - Dec 1986

Scopus Subject Areas

Software
Hardware and Architecture
Electrical and Electronic Engineering

User-Defined Keywords

Channel routing
compaction
vias

Access to Document

10.1016/0167-9260(86)90011-8

Cite this

@article{2b0a07884b6b4d65ad5a99b4346cd369,

title = "Compacted channel routing with via placement restrictions",

abstract = "We study in this paper the channel routing problem when there are restrictions on the placement of via holes. We show how to produce routing solutions that contain no horizontally adjacent vias and a close to minimum number of vertically and diagonally adjacent vias. Such solutions lead to compaction that will reduce total routing area.",

keywords = "Channel routing, compaction, vias",

author = "Wong, {D. F.} and Liu, {C. L.}",

note = "Funding Information: This work was partially supported by the Semiconductor Research Corporation under contract 84-06-049-4, by a grant from the General Electric Company, and by a grant from the Sandia Laboratories.",

year = "1986",

month = dec,

doi = "10.1016/0167-9260(86)90011-8",

language = "English",

volume = "4",

pages = "287--307",

journal = "Integration, the VLSI Journal",

issn = "0167-9260",

publisher = "Elsevier",

number = "4",

}

TY - JOUR

T1 - Compacted channel routing with via placement restrictions

AU - Wong, D. F.

AU - Liu, C. L.

N1 - Funding Information: This work was partially supported by the Semiconductor Research Corporation under contract 84-06-049-4, by a grant from the General Electric Company, and by a grant from the Sandia Laboratories.

PY - 1986/12

Y1 - 1986/12

N2 - We study in this paper the channel routing problem when there are restrictions on the placement of via holes. We show how to produce routing solutions that contain no horizontally adjacent vias and a close to minimum number of vertically and diagonally adjacent vias. Such solutions lead to compaction that will reduce total routing area.

AB - We study in this paper the channel routing problem when there are restrictions on the placement of via holes. We show how to produce routing solutions that contain no horizontally adjacent vias and a close to minimum number of vertically and diagonally adjacent vias. Such solutions lead to compaction that will reduce total routing area.

KW - Channel routing

KW - compaction

KW - vias

UR - http://www.scopus.com/inward/record.url?scp=0022890895&partnerID=8YFLogxK

U2 - 10.1016/0167-9260(86)90011-8

DO - 10.1016/0167-9260(86)90011-8

M3 - Journal article

AN - SCOPUS:0022890895

SN - 0167-9260

VL - 4

SP - 287

EP - 307

JO - Integration, the VLSI Journal

JF - Integration, the VLSI Journal

IS - 4

ER -

Compacted channel routing with via placement restrictions

Abstract

Scopus Subject Areas

User-Defined Keywords

Access to Document

Other files and links

Fingerprint

Cite this