Abstract
By putting different chips on the same mask, shuttle mask (or multiple project wafer) provides an economical solution for low volume designs and design prototypes to share the rising mask cost. A challenging floorplanning problem is to optimally pack these chips according to objectives and constraints related to cost and manufacturability. In this paper, we study the problem of CMP aware shuttle mask floorplanning, which is formulated as a rectangle packing problem with objectives of area and post-CMP topography variation minimization. We propose a 3-step procedure to solve the problem. First, we use the low-pass filter oxide CMP model to guide the simulated annealing search to minimize the topography variation. The result is then further improved by sliding each chip in its enclosing rectangle. Finally, we calculate the optimal amount of dummy feature needed with a linear programming method. Our experiment shows excellent results on real industry data.
Original language | English |
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Title of host publication | ASP-DAC '05 |
Subtitle of host publication | Proceedings of the 2005 Asia and South Pacific Design Automation Conference |
Place of Publication | United States |
Publisher | Association for Computing Machinery (ACM) |
Pages | 1111-1114 |
Number of pages | 4 |
ISBN (Electronic) | 9780780387379 |
ISBN (Print) | 0780387368, 9780780387362 |
DOIs | |
Publication status | Published - Jan 2005 |
Event | 10th Asia and South Pacific Design Automation Conference, ASP-DAC 2005 - Hotel Equatorial, Shanghai, China Duration: 18 Jan 2005 → 21 Jan 2005 https://www.aspdac.com/aspdac2005/ (Conference website) |
Publication series
Name | Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC |
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Conference
Conference | 10th Asia and South Pacific Design Automation Conference, ASP-DAC 2005 |
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Country/Territory | China |
City | Shanghai |
Period | 18/01/05 → 21/01/05 |
Internet address |
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