@inbook{dc3951238f4641e4ab546b446dc70166,
title = "Clustering and load balancing for buffered clock tree synthesis",
abstract = "Buffers in clock trees introduce two additional sources of skew: The first source of skew is the effect of process variations on buffer delays. The second source of skew is the imbalance in buffer loading. We propose a buffered clock tree synthesis methodology whereby we first apply a clustering algorithm to obtain clusters of approximately equal capacitance loading. We drive each of these clusters with identical buffers. A sensitivity based approach is then used for equalizing the Elmore delay from the buffer output to all of the clock nodes. The skew due to load imbalance is minimized concurrently by matching a higher-order model of the load by wire sizing and wire lengthening. We demonstrate how this algorithm can be used recursively to generate low-skew buffered clock trees.",
author = "Mehta, {Ashish D.} and Yao-Ping Chen and Noel Menezes and D.F. Wong and Pileggi, {Lawrence T.}",
note = "Funding Information: This work was supported in part by the Semiconductor Research Corporation under contract 95-DJ-343, the National Science Foundation under contract MIP-9157263, and IBM Corporation Publisher Copyright: {\textcopyright} 1997 IEEE; 1997 IEEE International Conference on Computer Design, ICCD 1997: VLSI in Computers and Processors ; Conference date: 12-10-1997 Through 15-10-1997",
year = "1997",
month = oct,
doi = "10.1109/ICCD.1997.628871",
language = "English",
isbn = "081868206X",
series = "Proceedings of 1997 IEEE International Conference on Computer Design, ICCD 1997: VLSI in Computers and Processors",
publisher = "IEEE",
pages = "217--223",
booktitle = "1997 IEEE International Conference on Computer Design, ICCD 1997: VLSI in Computers and Processors",
address = "United States",
}