Clustering and load balancing for buffered clock tree synthesis

Ashish D. Mehta, Yao-Ping Chen, Noel Menezes, D.F. Wong, Lawrence T. Pileggi

Research output: Chapter in book/report/conference proceedingChapterpeer-review

32 Citations (Scopus)

Abstract

Buffers in clock trees introduce two additional sources of skew: The first source of skew is the effect of process variations on buffer delays. The second source of skew is the imbalance in buffer loading. We propose a buffered clock tree synthesis methodology whereby we first apply a clustering algorithm to obtain clusters of approximately equal capacitance loading. We drive each of these clusters with identical buffers. A sensitivity based approach is then used for equalizing the Elmore delay from the buffer output to all of the clock nodes. The skew due to load imbalance is minimized concurrently by matching a higher-order model of the load by wire sizing and wire lengthening. We demonstrate how this algorithm can be used recursively to generate low-skew buffered clock trees.

Original languageEnglish
Title of host publication1997 IEEE International Conference on Computer Design, ICCD 1997: VLSI in Computers and Processors
PublisherIEEE
Pages217-223
Number of pages7
ISBN (Print)081868206X
DOIs
Publication statusPublished - Oct 1997
Event1997 IEEE International Conference on Computer Design, ICCD 1997: VLSI in Computers and Processors - Austin, United States
Duration: 12 Oct 199715 Oct 1997

Publication series

NameProceedings of 1997 IEEE International Conference on Computer Design, ICCD 1997: VLSI in Computers and Processors

Conference

Conference1997 IEEE International Conference on Computer Design, ICCD 1997: VLSI in Computers and Processors
Country/TerritoryUnited States
CityAustin
Period12/10/9715/10/97

Scopus Subject Areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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