Clustering and Binding Flip-Flops in Global Placement with Analytical Optimization

Modern Integrated Circuits (ICs) have obtained remarkable performance due to high integration density. Many challenges arose consequently as the circuit size expanded rapidly, causing severe quality degradation of the circuits. Power optimization has been a bottleneck for circuit design for a long time, and is becoming increasingly expensive for advanced technology nodes. The clock power contributes a large part of the power consumption, which is usually caused by long clock tree wirelength. Thus, the flip-flop clustering becomes an effective method to reduce the clock wirelength. Advanced technology introduced Multi-Bit Flip-Flop to further reduce the clock network size and power consumption. In this paper, we adopt the Multi-Bit Flip-Flop technology and propose an analytical placement framework for flip-flop clustering and binding optimization. A balanced clustering method is proposed to perform the Multi-Bit Flip-Flop generation. Experimental results show that our methods significantly outperform the state-of-the-art OpenROAD flows in terms of timing, power and clock tree construction.