Closed form solutions to simultaneous buffer insertion/sizing and wire sizing

Chris Chu, D. F. Wong

Research output: Contribution to journalJournal articlepeer-review

52 Citations (Scopus)


In this paper, we consider the delay minimization problem of an interconnect wire by simultaneously considering buffer insertion, buffer sizing and wire sizing. We consider three cases, namely using no buffer (i.e., wire sizing alone), using a given number of buffers, and using the optimal number of buffers. We provide elegant closed form optimal solutions for all three problems. These closed form solutions are useful in early stages of the VLSI design flow such as logic synthesis and floorplanning.

Original languageEnglish
Pages (from-to)343-371
Number of pages29
JournalACM Transactions on Design Automation of Electronic Systems
Issue number3
Publication statusPublished - Jul 2001

Scopus Subject Areas

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

User-Defined Keywords

  • Buffer insertion
  • Buffer sizing
  • Closed form solution
  • Interconnect optimization
  • Wire sizing


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