Clock skew minimization during FPGA placement

Unlike traditional ASIC technologies, the geometrical structures of clock trees in an FPGA are usually fixed and cannot be changed for different circuit designs. Moreover, the clock pins are connected to the clock trees via programmable switches. As a result, the load capacitances of a clock tree may be changed, depending on the utilization and distribution of logic modules in an FPGA. It is possible to minimize clock skew by distributing the load capacitances, or equivalently the logic modules used by the circuit design, carefully according to the circuit design. In this paper we present an algorithm for selecting logic modules used for circuit placement such that the clock skew is minimized. The algorithm can be applied to a variety of clock tree architectures, including those used in major commercial FPGAs. Furthermore, the algorithm can be extended to handle buffered clock trees and multi-phase clock trees. Experimental results show that the algorithm can reduce clock skews significantly as compared with the traditional placement algorithms which do not consider clock skew minimization.