Clock skew minimization during FPGA placement

Kai Zhu, D. F. Wong

Research output: Chapter in book/report/conference proceedingChapterpeer-review

5 Citations (Scopus)


Unlike traditional ASIC technologies, the geometrical structures of clock trees in an FPGA are usually fixed and cannot be changed for different circuit designs. Moreover, the clock pins are connected to the clock trees via programmable switches. As a result, the load capacitances of a clock tree may be changed, depending on the utilization and distribution of logic modules in an FPGA. It is possible to minimize clock skew by distributing the load capacitances, or equivalently the logic modules used by the circuit design, carefully according to the circuit design. In this paper we present an algorithm for selecting logic modules used for circuit placement such that the clock skew is minimized. The algorithm can be applied to a variety of clock tree architectures, including those used in major commercial FPGAs. Furthermore, the algorithm can be extended to handle buffered clock trees and multi-phase clock trees. Experimental results show that the algorithm can reduce clock skews significantly as compared with the traditional placement algorithms which do not consider clock skew minimization.

Original languageEnglish
Title of host publication31st ACM/IEEE Design Automation Conference - Proceedings 1994
PublisherAssociation for Computing Machinery (ACM)
Number of pages6
ISBN (Print)9780897916530, 0897916530
Publication statusPublished - Jun 1994
Event31st ACM/IEEE-CAS/EDAC Design Automation Conference, DAC 1994 - San Diego, United States
Duration: 6 Jun 199410 Jun 1994 (Link to conference proceedings)

Publication series

NameACM/IEEE Design Automation Conference - Proceedings
ISSN (Print)0738-100X


Conference31st ACM/IEEE-CAS/EDAC Design Automation Conference, DAC 1994
Country/TerritoryUnited States
CitySan Diego
Internet address

Scopus Subject Areas

  • Hardware and Architecture
  • Control and Systems Engineering


Dive into the research topics of 'Clock skew minimization during FPGA placement'. Together they form a unique fingerprint.

Cite this