Circuit partitioning for dynamically reconfigurable FPGAs

Huiqun Liu*, D. F. Wong

*Corresponding author for this work

Research output: Chapter in book/report/conference proceedingConference proceedingpeer-review

19 Citations (Scopus)

Abstract

Dynamically reconfigurable FPGAs have the potential to dramatically improve logic density by time-sharing a physical FPGA device. This paper presents a network-flow based partitioning algorithm for dynamically reconfigurable FPGAs based on the architecture in [2]. Experiments show that our approach outperforms the enhanced force-directed scheduling method in [2] in terms of communication cost.

Original languageEnglish
Title of host publicationFPGA '99
Subtitle of host publicationProceedings of the 7th ACM/SIGDA International Symposium on Field Programmable Gate Arrays
PublisherAssociation for Computing Machinery (ACM)
Pages187-194
Number of pages8
ISBN (Print)9781581130881
DOIs
Publication statusPublished - 21 Feb 1999
Event7th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 1999 - Monterey, United States
Duration: 21 Feb 199923 Feb 1999
https://dl.acm.org/doi/proceedings/10.1145/296399

Publication series

NameProceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA

Conference

Conference7th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 1999
Country/TerritoryUnited States
CityMonterey
Period21/02/9923/02/99
Internet address

Scopus Subject Areas

  • Computer Science(all)

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