Circuit partitioning for dynamically reconfigurable FPGAs

Huiqun Liu; D. F. Wong

doi:10.1145/296399.296456

Circuit partitioning for dynamically reconfigurable FPGAs

Huiqun Liu^*, D. F. Wong

^*Corresponding author for this work

Office of the Provost

Research output: Chapter in book/report/conference proceeding › Conference proceeding › peer-review

19 Citations (Scopus)

Abstract

Dynamically reconfigurable FPGAs have the potential to dramatically improve logic density by time-sharing a physical FPGA device. This paper presents a network-flow based partitioning algorithm for dynamically reconfigurable FPGAs based on the architecture in [2]. Experiments show that our approach outperforms the enhanced force-directed scheduling method in [2] in terms of communication cost.

Original language	English
Title of host publication	FPGA '99
Subtitle of host publication	Proceedings of the 7th ACM/SIGDA International Symposium on Field Programmable Gate Arrays
Publisher	Association for Computing Machinery (ACM)
Pages	187-194
Number of pages	8
ISBN (Print)	9781581130881
DOIs	https://doi.org/10.1145/296399.296456
Publication status	Published - 21 Feb 1999
Event	7th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 1999 - Monterey, United States Duration: 21 Feb 1999 → 23 Feb 1999 https://dl.acm.org/doi/proceedings/10.1145/296399

Publication series

Name	Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA

Conference

Conference	7th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 1999
Country/Territory	United States
City	Monterey
Period	21/02/99 → 23/02/99
Internet address	https://dl.acm.org/doi/proceedings/10.1145/296399

Scopus Subject Areas

General Computer Science

Access to Document

10.1145/296399.296456

Cite this

Liu, H., & Wong, D. F. (1999). Circuit partitioning for dynamically reconfigurable FPGAs. In FPGA '99: Proceedings of the 7th ACM/SIGDA International Symposium on Field Programmable Gate Arrays (pp. 187-194). (Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA). Association for Computing Machinery (ACM). https://doi.org/10.1145/296399.296456

@inproceedings{d3f63127a8084a70a4b32a2b376f1b67,

title = "Circuit partitioning for dynamically reconfigurable FPGAs",

abstract = "Dynamically reconfigurable FPGAs have the potential to dramatically improve logic density by time-sharing a physical FPGA device. This paper presents a network-flow based partitioning algorithm for dynamically reconfigurable FPGAs based on the architecture in [2]. Experiments show that our approach outperforms the enhanced force-directed scheduling method in [2] in terms of communication cost.",

author = "Huiqun Liu and Wong, {D. F.}",

note = "This work was partially supported by the Texas Advanced Research Program under Grant No. 003658288.; 7th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 1999 ; Conference date: 21-02-1999 Through 23-02-1999",

year = "1999",

month = feb,

day = "21",

doi = "10.1145/296399.296456",

language = "English",

isbn = "9781581130881",

series = "Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA",

publisher = "Association for Computing Machinery (ACM)",

pages = "187--194",

booktitle = "FPGA '99",

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url = "https://dl.acm.org/doi/proceedings/10.1145/296399",

}

Liu, H & Wong, DF 1999, Circuit partitioning for dynamically reconfigurable FPGAs. in FPGA '99: Proceedings of the 7th ACM/SIGDA International Symposium on Field Programmable Gate Arrays. Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA, Association for Computing Machinery (ACM), pp. 187-194, 7th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 1999, Monterey, California, United States, 21/02/99. https://doi.org/10.1145/296399.296456

Circuit partitioning for dynamically reconfigurable FPGAs. / Liu, Huiqun; Wong, D. F.
FPGA '99: Proceedings of the 7th ACM/SIGDA International Symposium on Field Programmable Gate Arrays. Association for Computing Machinery (ACM), 1999. p. 187-194 (Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA).

Research output: Chapter in book/report/conference proceeding › Conference proceeding › peer-review

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AU - Wong, D. F.

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Y1 - 1999/2/21

N2 - Dynamically reconfigurable FPGAs have the potential to dramatically improve logic density by time-sharing a physical FPGA device. This paper presents a network-flow based partitioning algorithm for dynamically reconfigurable FPGAs based on the architecture in [2]. Experiments show that our approach outperforms the enhanced force-directed scheduling method in [2] in terms of communication cost.

AB - Dynamically reconfigurable FPGAs have the potential to dramatically improve logic density by time-sharing a physical FPGA device. This paper presents a network-flow based partitioning algorithm for dynamically reconfigurable FPGAs based on the architecture in [2]. Experiments show that our approach outperforms the enhanced force-directed scheduling method in [2] in terms of communication cost.

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ER -

Circuit partitioning for dynamically reconfigurable FPGAs

Abstract

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