Circuit clustering for delay minimization under area and pin constraints

Keyphrases

• Area Constraint 100%
• Array chip 20%
• Benchmark Circuits 20%
• Chip Implementation 20%
• Circuit Delay 40%
• Circuit Partitioning 40%
• Clustering Algorithm 20%
• Current Needs 20%
• Delay Minimization 100%
• Delay Model 20%
• Duplication 40%
• Field Programmable Gate Arrays 20%
• General Delay 20%
• Logic Gates 40%
• Motivation 20%
• Multiple chips 20%
• Multiple Fields 20%
• Near-optimal 20%
• Network Cut 20%
• Non-optimality 20%
• Optimal Delay 60%
• Pin Constraint 100%

Computer Science

• Area Constraint 50%
• Benchmark Circuit 50%
• Clustering Algorithm 50%
• Delay Minimization 100%
• Field Programmable Gate Array 50%
• Logic Gate 100%