Abstract
We consider the problem of circuit partitioning for multiple-chip implementation. One motivation for studying this problem is the current needs of good partitioning tools for implementing a circuit on multiple FPGA chips. We allow duplication of logic gates as it would reduce circuit delay. Circuit partitioning with duplication of logic gates is also called circuit clustering. In this paper, we present a circuit clustering algorithm that minimizes circuit delay subject to both area and pin constraints on each chip, using the general delay model. We develop a repeated network cut technique for finding a cluster that is bounded by both area and pin constraints. Our algorithm achieves optimal delay under either the area constraint only or the pin constraint only. Under both area and pin constraints, our algorithm achieves optimal delay in most cases. We outline the condition under which the nonoptimality occurs and show that the condition occurs rarely in practice. We tested our algorithm on a set of benchmark circuits and consistently obtained optimal or near-optimal delays.
Original language | English |
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Title of host publication | 1995 European Conference on Design and Test, EDTC 1995 |
Publisher | IEEE |
Pages | 65-70 |
Number of pages | 6 |
ISBN (Electronic) | 0818670398 |
DOIs | |
Publication status | Published - Mar 1995 |
Event | 1995 European Conference on Design and Test, EDTC 1995 - Paris, France Duration: 6 Mar 1995 → 9 Mar 1995 https://ieeexplore.ieee.org/xpl/conhome/3300/proceeding (Link to conference proceedings) |
Publication series
Name | Proceedings of 1995 European Conference on Design and Test, EDTC 1995 |
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Conference
Conference | 1995 European Conference on Design and Test, EDTC 1995 |
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Country/Territory | France |
City | Paris |
Period | 6/03/95 → 9/03/95 |
Internet address |
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Scopus Subject Areas
- Hardware and Architecture
- Electrical and Electronic Engineering
- Industrial and Manufacturing Engineering