In this paper we study the problem of routing region definition and ordering in VLSI building-block layout design. We present an algorithm to decompose the routing area into straight channels and rectangular switchboxes such that the number of switchboxes is minimized. Our algorithm is based on a graph-theory approach that makes use of an efficient polynomial time algorithm for computing minimum clique covers of triangulated graphs. Experimental results indicate that our algorithm performs well. For all the test problems we considered, our algorithm consistently outperformed a previous known greedy algorithm, and it produced optimal solutions in all but one case.
|Number of pages||9|
|Journal||IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems|
|Publication status||Published - Dec 1991|
Scopus Subject Areas
- Computer Graphics and Computer-Aided Design
- Electrical and Electronic Engineering