Channel segmentation design for symmetrical FPGAs

Wai-Kei Mak, D. F. Wong

Research output: Chapter in book/report/conference proceedingChapterpeer-review

7 Citations (Scopus)

Abstract

The channel segmentation design problem for symmetrical FPGAs is the problem of designing segmented tracks in the interconnection channels that provides good net routability and delay performance at the same time. In this paper, we show how to separate the problem into the segmentation design problems of the vertical and horizontal channels by a statistical analysis of the net distribution on a symmetrical FPGA. And we propose an effective approach for segmented channel design when the allowed number of tracks in a channel is fixed and limited.

Original languageEnglish
Title of host publication1997 IEEE International Conference on Computer Design, ICCD 1997: VLSI in Computers and Processors
PublisherIEEE
Pages496-501
Number of pages6
ISBN (Print)081868206X
DOIs
Publication statusPublished - Oct 1997
Event1997 IEEE International Conference on Computer Design, ICCD 1997: VLSI in Computers and Processors - Austin, United States
Duration: 12 Oct 199715 Oct 1997

Publication series

NameProceedings of 1997 IEEE International Conference on Computer Design, ICCD 1997: VLSI in Computers and Processors

Conference

Conference1997 IEEE International Conference on Computer Design, ICCD 1997: VLSI in Computers and Processors
Country/TerritoryUnited States
CityAustin
Period12/10/9715/10/97

Scopus Subject Areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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