Cell area minimization by transistor folding

T.W. Her; D.F. Wong

doi:10.1109/EURDAC.1993.410633

Cell area minimization by transistor folding

T.W. Her, D.F. Wong

Office of the Provost

Research output: Chapter in book/report/conference proceeding › Conference proceeding

7 Citations (Scopus)

Abstract

Tall transistors can be folded into shorter ones to reduce the layout area. The authors take two rows of transistors, one for P-type transistors and the other for N-type transistors, and attempt to determine an optimal folding for each transistor to minimize the layout area. They present an O(K/sup 3/L/sup 3/) time transistor folding algorithm to minimize the layout area, where K is the number of implementations of each transistor due to folding, and L is the channel length.

Original language	English
Title of host publication	Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference
Publisher	IEEE
Pages	172-177
Number of pages	6
ISBN (Print)	0818643501
DOIs	https://doi.org/10.1109/EURDAC.1993.410633
Publication status	Published - 24 Sept 1993
Event	EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference - Hamburg, Germany Duration: 20 Sept 1993 → 24 Sept 1993 https://ieeexplore.ieee.org/xpl/conhome/3227/proceeding

Publication series

Name	European Design Automation Conference

Conference

Conference	EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference
Country/Territory	Germany
City	Hamburg
Period	20/09/93 → 24/09/93
Internet address	https://ieeexplore.ieee.org/xpl/conhome/3227/proceeding

User-Defined Keywords

Circuits
Electric variables
MOS devices
Routing

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10.1109/EURDAC.1993.410633

Cite this

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title = "Cell area minimization by transistor folding",

abstract = "Tall transistors can be folded into shorter ones to reduce the layout area. The authors take two rows of transistors, one for P-type transistors and the other for N-type transistors, and attempt to determine an optimal folding for each transistor to minimize the layout area. They present an O(K/sup 3/L/sup 3/) time transistor folding algorithm to minimize the layout area, where K is the number of implementations of each transistor due to folding, and L is the channel length.",

keywords = "Circuits, Electric variables, MOS devices, Routing",

author = "T.W. Her and D.F. Wong",

year = "1993",

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language = "English",

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note = "EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference ; Conference date: 20-09-1993 Through 24-09-1993",

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T1 - Cell area minimization by transistor folding

AU - Her, T.W.

AU - Wong, D.F.

PY - 1993/9/24

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N2 - Tall transistors can be folded into shorter ones to reduce the layout area. The authors take two rows of transistors, one for P-type transistors and the other for N-type transistors, and attempt to determine an optimal folding for each transistor to minimize the layout area. They present an O(K/sup 3/L/sup 3/) time transistor folding algorithm to minimize the layout area, where K is the number of implementations of each transistor due to folding, and L is the channel length.

AB - Tall transistors can be folded into shorter ones to reduce the layout area. The authors take two rows of transistors, one for P-type transistors and the other for N-type transistors, and attempt to determine an optimal folding for each transistor to minimize the layout area. They present an O(K/sup 3/L/sup 3/) time transistor folding algorithm to minimize the layout area, where K is the number of implementations of each transistor due to folding, and L is the channel length.

KW - Circuits

KW - Electric variables

KW - MOS devices

KW - Routing

UR - https://ieeexplore.ieee.org/document/410633/

U2 - 10.1109/EURDAC.1993.410633

DO - 10.1109/EURDAC.1993.410633

M3 - Conference proceeding

SN - 0818643501

T3 - European Design Automation Conference

SP - 172

EP - 177

BT - Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference

PB - IEEE

T2 - EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference

Y2 - 20 September 1993 through 24 September 1993

ER -

Cell area minimization by transistor folding

Abstract

Publication series

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