TY - JOUR
T1 - Bus-driven floorplanning
AU - Xiang, Hua
AU - Tang, Xiaoping
AU - Wong, Martin D. F.
N1 - Funding Information:
This work was supported in part by the National Science Foundation under Grant CCR0244236 and Grant CCR-0306244. This paper was recommended by Associate Editor T. Yoshimura.
Publisher copyright:
© 2004 IEEE
PY - 2004/11
Y1 - 2004/11
N2 - In this paper, we present an integrated approach for floorplanning and bus planning, i.e., bus-driven floorplanning (BDF). We are given a set of circuit blocks and the bus specifications (i.e., the net list of blocks for the buses). A feasible BDF solution is a placement of all circuit blocks such that each bus can be realized as a rectangular strip (horizontal or vertical) going through all the blocks connected by the bus. The objective is to determine a feasible BDF solution that minimizes the floorplan area and the total bus area. Our approach is based upon the sequence-pair floorplan representation. After a careful analysis of the relationship between bus ordering and block ordering in the floorplan represented by a sequence pair, we derive feasibility conditions on sequence pairs that give feasible BDF solutions. Experimental results demonstrate the efficiency and effectiveness of our algorithm.
AB - In this paper, we present an integrated approach for floorplanning and bus planning, i.e., bus-driven floorplanning (BDF). We are given a set of circuit blocks and the bus specifications (i.e., the net list of blocks for the buses). A feasible BDF solution is a placement of all circuit blocks such that each bus can be realized as a rectangular strip (horizontal or vertical) going through all the blocks connected by the bus. The objective is to determine a feasible BDF solution that minimizes the floorplan area and the total bus area. Our approach is based upon the sequence-pair floorplan representation. After a careful analysis of the relationship between bus ordering and block ordering in the floorplan represented by a sequence pair, we derive feasibility conditions on sequence pairs that give feasible BDF solutions. Experimental results demonstrate the efficiency and effectiveness of our algorithm.
KW - Computer-aided design (CAD)
KW - Floorplan
KW - Physical design
KW - Sequence pair
KW - Very large scale integration (VLSI)
UR - http://www.scopus.com/inward/record.url?scp=8344272834&partnerID=8YFLogxK
U2 - 10.1109/TCAD.2004.836728
DO - 10.1109/TCAD.2004.836728
M3 - Journal article
AN - SCOPUS:8344272834
SN - 0278-0070
VL - 23
SP - 1522
EP - 1530
JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IS - 11
ER -