Automatic bus planner for dense PCBs

Kong Hui; Yan Tan; Martin D. F. Wong

doi:10.1145/1629911.1630000

Automatic bus planner for dense PCBs

Kong Hui, Yan Tan, Martin D. F. Wong

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Research output: Chapter in book/report/conference proceeding › Conference proceeding › peer-review

29 Citations (Scopus)

Abstract

Since no commercial PCB routing tools can solve the routing problem for today's complex PCBs, these circuit boards have to be routed manually, taking about 2 months of time per board. Bus planning is one of the most time-consuming steps of PCB routing. It consists of assigning buses to multiple layers of the PCB and routing them in a planar fashion on each layer. Routing congestion between on-board components and the min-max length bounds of the buses must also be considered during routing. In this paper, we present the first automatic bus planner. We tested our system on a state-of-the-art industrial circuit board with over 7000 nets and 12 signal layers. All the nets on this board were already manually routed. Our bus planner is able to achieve 100% routing completion using the layer assignment extracted from manual design. For simultaneous layer assignment and bus routing, we are able to successfully route 98.5% of the nets. The remaining 1.5% can be routed either manually or by using vias. The runtime of our bus planner is less than 3 hours on a 3 Ghz workstation.

Original language	English
Title of host publication	46th ACM/IEEE Design Automation Conference - Proceedings 2009
Publisher	Association for Computing Machinery (ACM)
Pages	326-331
Number of pages	6
ISBN (Print)	9781605584973
DOIs	https://doi.org/10.1145/1629911.1630000
Publication status	Published - 29 Jul 2009
Event	46th ACM/IEEE Design Automation Conference, DAC 2009 - San Francisco, United States Duration: 26 Jul 2009 → 31 Jul 2009 https://www.dac.com/About/Conference-Archive/46th-DAC-2009 (Conference website) https://www.dac.com/portals/0/documents/archive/2009/46DAC_Final_Prgm.pdf (Conference programme ) https://dl.acm.org/doi/proceedings/10.1145/1629911 (Conference proceedings) https://ieeexplore.ieee.org/xpl/conhome/5209519/proceeding

Publication series

Name	ACM/IEEE Design Automation Conference - Proceedings
ISSN (Print)	0738-100X

Conference

Conference	46th ACM/IEEE Design Automation Conference, DAC 2009
Country/Territory	United States
City	San Francisco
Period	26/07/09 → 31/07/09
Internet address	https://www.dac.com/About/Conference-Archive/46th-DAC-2009 (Conference website) https://www.dac.com/portals/0/documents/archive/2009/46DAC_Final_Prgm.pdf (Conference programme ) https://dl.acm.org/doi/proceedings/10.1145/1629911 (Conference proceedings) https://ieeexplore.ieee.org/xpl/conhome/5209519/proceeding

Scopus Subject Areas

Computer Science Applications
Control and Systems Engineering
Electrical and Electronic Engineering
Modelling and Simulation

User-Defined Keywords

Topological Routing
Layer Assignment
Bus Planning
PCB Routing

Access to Document

10.1145/1629911.1630000

Cite this

@inproceedings{35052195541245a3846413074f9e8b65,

title = "Automatic bus planner for dense PCBs",

abstract = "Since no commercial PCB routing tools can solve the routing problem for today's complex PCBs, these circuit boards have to be routed manually, taking about 2 months of time per board. Bus planning is one of the most time-consuming steps of PCB routing. It consists of assigning buses to multiple layers of the PCB and routing them in a planar fashion on each layer. Routing congestion between on-board components and the min-max length bounds of the buses must also be considered during routing. In this paper, we present the first automatic bus planner. We tested our system on a state-of-the-art industrial circuit board with over 7000 nets and 12 signal layers. All the nets on this board were already manually routed. Our bus planner is able to achieve 100% routing completion using the layer assignment extracted from manual design. For simultaneous layer assignment and bus routing, we are able to successfully route 98.5% of the nets. The remaining 1.5% can be routed either manually or by using vias. The runtime of our bus planner is less than 3 hours on a 3 Ghz workstation.",

keywords = "Topological Routing, Layer Assignment, Bus Planning, PCB Routing",

author = "Kong Hui and Yan Tan and Wong, {Martin D. F.}",

note = "Funding Information: This work has been supported in part by CNR, Progetto Finalizzato Chimica Fine.; 46th ACM/IEEE Design Automation Conference, DAC 2009 ; Conference date: 26-07-2009 Through 31-07-2009",

year = "2009",

month = jul,

day = "29",

doi = "10.1145/1629911.1630000",

language = "English",

isbn = "9781605584973",

series = "ACM/IEEE Design Automation Conference - Proceedings",

publisher = "Association for Computing Machinery (ACM)",

pages = "326--331",

booktitle = "46th ACM/IEEE Design Automation Conference - Proceedings 2009",

address = "United States",

url = "https://www.dac.com/About/Conference-Archive/46th-DAC-2009, https://www.dac.com/portals/0/documents/archive/2009/46DAC_Final_Prgm.pdf, https://dl.acm.org/doi/proceedings/10.1145/1629911, https://ieeexplore.ieee.org/xpl/conhome/5209519/proceeding",

}

Hui, K, Tan, Y & Wong, MDF 2009, Automatic bus planner for dense PCBs. in 46th ACM/IEEE Design Automation Conference - Proceedings 2009. ACM/IEEE Design Automation Conference - Proceedings, Association for Computing Machinery (ACM), pp. 326-331, 46th ACM/IEEE Design Automation Conference, DAC 2009, San Francisco, California, United States, 26/07/09. https://doi.org/10.1145/1629911.1630000

TY - GEN

T1 - Automatic bus planner for dense PCBs

AU - Hui, Kong

AU - Tan, Yan

AU - Wong, Martin D. F.

N1 - Funding Information: This work has been supported in part by CNR, Progetto Finalizzato Chimica Fine.

PY - 2009/7/29

Y1 - 2009/7/29

N2 - Since no commercial PCB routing tools can solve the routing problem for today's complex PCBs, these circuit boards have to be routed manually, taking about 2 months of time per board. Bus planning is one of the most time-consuming steps of PCB routing. It consists of assigning buses to multiple layers of the PCB and routing them in a planar fashion on each layer. Routing congestion between on-board components and the min-max length bounds of the buses must also be considered during routing. In this paper, we present the first automatic bus planner. We tested our system on a state-of-the-art industrial circuit board with over 7000 nets and 12 signal layers. All the nets on this board were already manually routed. Our bus planner is able to achieve 100% routing completion using the layer assignment extracted from manual design. For simultaneous layer assignment and bus routing, we are able to successfully route 98.5% of the nets. The remaining 1.5% can be routed either manually or by using vias. The runtime of our bus planner is less than 3 hours on a 3 Ghz workstation.

AB - Since no commercial PCB routing tools can solve the routing problem for today's complex PCBs, these circuit boards have to be routed manually, taking about 2 months of time per board. Bus planning is one of the most time-consuming steps of PCB routing. It consists of assigning buses to multiple layers of the PCB and routing them in a planar fashion on each layer. Routing congestion between on-board components and the min-max length bounds of the buses must also be considered during routing. In this paper, we present the first automatic bus planner. We tested our system on a state-of-the-art industrial circuit board with over 7000 nets and 12 signal layers. All the nets on this board were already manually routed. Our bus planner is able to achieve 100% routing completion using the layer assignment extracted from manual design. For simultaneous layer assignment and bus routing, we are able to successfully route 98.5% of the nets. The remaining 1.5% can be routed either manually or by using vias. The runtime of our bus planner is less than 3 hours on a 3 Ghz workstation.

KW - Topological Routing

KW - Layer Assignment

KW - Bus Planning

KW - PCB Routing

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T3 - ACM/IEEE Design Automation Conference - Proceedings

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BT - 46th ACM/IEEE Design Automation Conference - Proceedings 2009

PB - Association for Computing Machinery (ACM)

T2 - 46th ACM/IEEE Design Automation Conference, DAC 2009

Y2 - 26 July 2009 through 31 July 2009

ER -

Automatic bus planner for dense PCBs

Abstract

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Conference

Scopus Subject Areas

User-Defined Keywords

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