Array optimization for VLSI synthesis

D. F. Wong*, C. L. Liu

*Corresponding author for this work

Research output: Chapter in book/report/conference proceedingConference proceedingpeer-review


We present in this paper an algorithm that solves a general array optimization problem. The algorithm can be used for compacting Gate Matrix layouts, SLA's, Weinberger Arrays, and for multiple folding of PLA's. Our approach is based on the technique of simulated annealing. A major contribution of this paper is the formulation of the solution space which facilitates an effective search for an optimal solution. Experimental results are very encouraging.

Original languageEnglish
Title of host publication24th ACM/IEEE Design Automation Conference - Proceedings 1987
Number of pages7
ISBN (Print)0818607815, 9780818607813, 0897912349
Publication statusPublished - Oct 1987
Event24th ACM/IEEE Design Automation Conference, DAC 1987 - Miami Beach, FL, United States
Duration: 28 Jun 19871 Jul 1987

Publication series

NameACM/IEEE Design Automation Conference - Proceedings
ISSN (Print)0738-100X


Conference24th ACM/IEEE Design Automation Conference, DAC 1987
Country/TerritoryUnited States
CityMiami Beach, FL
Internet address

Scopus Subject Areas

  • Engineering(all)


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