Array optimization for VLSI synthesis

D. F. Wong; C. L. Liu

doi:10.1145/37888.37968

Array optimization for VLSI synthesis

D. F. Wong^*, C. L. Liu

^*Corresponding author for this work

Office of the Provost

Research output: Chapter in book/report/conference proceeding › Conference proceeding › peer-review

Abstract

We present in this paper an algorithm that solves a general array optimization problem. The algorithm can be used for compacting Gate Matrix layouts, SLA's, Weinberger Arrays, and for multiple folding of PLA's. Our approach is based on the technique of simulated annealing. A major contribution of this paper is the formulation of the solution space which facilitates an effective search for an optimal solution. Experimental results are very encouraging.

Original language	English
Title of host publication	24th ACM/IEEE Design Automation Conference - Proceedings 1987
Publisher	IEEE
Pages	537-543
Number of pages	7
ISBN (Print)	0818607815, 9780818607813, 0897912349
DOIs	https://doi.org/10.1145/37888.37968
Publication status	Published - Oct 1987
Event	24th ACM/IEEE Design Automation Conference, DAC 1987 - Miami Beach, FL, United States Duration: 28 Jun 1987 → 1 Jul 1987 https://ieeexplore.ieee.org/xpl/conhome/10573/proceeding https://dl.acm.org/doi/proceedings/10.1145/37888

Publication series

Name	ACM/IEEE Design Automation Conference - Proceedings
ISSN (Print)	0738-100X

Conference

Conference	24th ACM/IEEE Design Automation Conference, DAC 1987
Country/Territory	United States
City	Miami Beach, FL
Period	28/06/87 → 1/07/87
Internet address	https://ieeexplore.ieee.org/xpl/conhome/10573/proceeding https://dl.acm.org/doi/proceedings/10.1145/37888

Scopus Subject Areas

Engineering(all)

Access to Document

10.1145/37888.37968

Cite this

@inproceedings{f57fb02b2c8d412d94ac584ec66a6eb5,

title = "Array optimization for VLSI synthesis",

abstract = "We present in this paper an algorithm that solves a general array optimization problem. The algorithm can be used for compacting Gate Matrix layouts, SLA's, Weinberger Arrays, and for multiple folding of PLA's. Our approach is based on the technique of simulated annealing. A major contribution of this paper is the formulation of the solution space which facilitates an effective search for an optimal solution. Experimental results are very encouraging.",

author = "Wong, {D. F.} and Liu, {C. L.}",

note = "This work was partially supported by the Semiconductor Research Corporation under contract 86-12-109, by a grant from the General Electric Company, and by a grant from the Sandra Laboratories.; 24th ACM/IEEE Design Automation Conference, DAC 1987 ; Conference date: 28-06-1987 Through 01-07-1987",

year = "1987",

month = oct,

doi = "10.1145/37888.37968",

language = "English",

isbn = "0818607815",

series = "ACM/IEEE Design Automation Conference - Proceedings",

publisher = "IEEE",

pages = "537--543",

booktitle = "24th ACM/IEEE Design Automation Conference - Proceedings 1987",

address = "United States",

url = "https://ieeexplore.ieee.org/xpl/conhome/10573/proceeding, https://dl.acm.org/doi/proceedings/10.1145/37888",

}

TY - GEN

T1 - Array optimization for VLSI synthesis

AU - Wong, D. F.

AU - Liu, C. L.

N1 - This work was partially supported by the Semiconductor Research Corporation under contract 86-12-109, by a grant from the General Electric Company, and by a grant from the Sandra Laboratories.

PY - 1987/10

Y1 - 1987/10

N2 - We present in this paper an algorithm that solves a general array optimization problem. The algorithm can be used for compacting Gate Matrix layouts, SLA's, Weinberger Arrays, and for multiple folding of PLA's. Our approach is based on the technique of simulated annealing. A major contribution of this paper is the formulation of the solution space which facilitates an effective search for an optimal solution. Experimental results are very encouraging.

AB - We present in this paper an algorithm that solves a general array optimization problem. The algorithm can be used for compacting Gate Matrix layouts, SLA's, Weinberger Arrays, and for multiple folding of PLA's. Our approach is based on the technique of simulated annealing. A major contribution of this paper is the formulation of the solution space which facilitates an effective search for an optimal solution. Experimental results are very encouraging.

UR - https://dl.acm.org/doi/10.1145/37888.37968

UR - https://ieeexplore.ieee.org/document/1586278

UR - http://www.scopus.com/inward/record.url?scp=0023255062&partnerID=8YFLogxK

U2 - 10.1145/37888.37968

DO - 10.1145/37888.37968

M3 - Conference proceeding

AN - SCOPUS:0023255062

SN - 0818607815

SN - 9780818607813

SN - 0897912349

T3 - ACM/IEEE Design Automation Conference - Proceedings

SP - 537

EP - 543

BT - 24th ACM/IEEE Design Automation Conference - Proceedings 1987

PB - IEEE

T2 - 24th ACM/IEEE Design Automation Conference, DAC 1987

Y2 - 28 June 1987 through 1 July 1987

ER -

Array optimization for VLSI synthesis

Abstract

Publication series

Conference

Scopus Subject Areas

Access to Document

Other files and links

Fingerprint

Cite this