Area optimization for higher order hierarchical floorplans

Khe-Sing The, D.F. Wong

Research output: Chapter in book/report/conference proceedingConference proceeding

4 Citations (Scopus)

Abstract

The floorplan area optimization problem is to determine the dimensions of each module when the topology of the floorplan is given. The objective is to minimize the area of the resulting floorplan. An algorithm for general hierarchical floorplans is presented. The shape curves for non-slicing configurations are constructed by operations on the graph representations of the floorplan. The points of a shape curve are determined by simultaneously reducing the length of all longest paths of the vertical adjacency graph, using a minimum cut technique. The algorithm is applicable to hierarchical floorplans of high order and to modules with an infinite set of possible dimensions.
Original languageEnglish
Title of host publication[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors
PublisherIEEE
Pages520-523
Number of pages4
ISBN (Print)0818622709
DOIs
Publication statusPublished - 16 Oct 1991
Event1991 IEEE International Conference on Computer Design, ICCD 1991: VLSI in Computers and Processors - Cambridge, MA, United States
Duration: 14 Oct 199116 Oct 1991
https://ieeexplore.ieee.org/xpl/conhome/367/proceeding

Publication series

NameIEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD

Conference

Conference1991 IEEE International Conference on Computer Design, ICCD 1991
Country/TerritoryUnited States
CityCambridge, MA
Period14/10/9116/10/91
Internet address

User-Defined Keywords

  • Shape
  • Iterative algorithms
  • Piecewise linear techniques
  • Algorithm design and analysis
  • Flexible printed circuits
  • Circuit topology
  • Heuristic algorithms
  • Approximation algorithms
  • Piecewise linear approximation

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