Area optimization for higher order hierarchical floorplans

Khe-Sing The; D.F. Wong

doi:10.1109/ICCD.1991.139963

Area optimization for higher order hierarchical floorplans

Khe-Sing The, D.F. Wong

Office of the Provost

Research output: Chapter in book/report/conference proceeding › Conference proceeding

5 Citations (Scopus)

Abstract

The floorplan area optimization problem is to determine the dimensions of each module when the topology of the floorplan is given. The objective is to minimize the area of the resulting floorplan. An algorithm for general hierarchical floorplans is presented. The shape curves for non-slicing configurations are constructed by operations on the graph representations of the floorplan. The points of a shape curve are determined by simultaneously reducing the length of all longest paths of the vertical adjacency graph, using a minimum cut technique. The algorithm is applicable to hierarchical floorplans of high order and to modules with an infinite set of possible dimensions.

Original language	English
Title of host publication	[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors
Publisher	IEEE
Pages	520-523
Number of pages	4
ISBN (Print)	0818622709
DOIs	https://doi.org/10.1109/ICCD.1991.139963
Publication status	Published - 16 Oct 1991
Event	1991 IEEE International Conference on Computer Design, ICCD 1991: VLSI in Computers and Processors - Cambridge, MA, United States Duration: 14 Oct 1991 → 16 Oct 1991 https://ieeexplore.ieee.org/xpl/conhome/367/proceeding

Publication series

Name	IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD

Conference

Conference	1991 IEEE International Conference on Computer Design, ICCD 1991
Country/Territory	United States
City	Cambridge, MA
Period	14/10/91 → 16/10/91
Internet address	https://ieeexplore.ieee.org/xpl/conhome/367/proceeding

User-Defined Keywords

Shape
Iterative algorithms
Piecewise linear techniques
Algorithm design and analysis
Flexible printed circuits
Circuit topology
Heuristic algorithms
Approximation algorithms
Piecewise linear approximation

Access to Document

10.1109/ICCD.1991.139963

Cite this

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title = "Area optimization for higher order hierarchical floorplans",

abstract = "The floorplan area optimization problem is to determine the dimensions of each module when the topology of the floorplan is given. The objective is to minimize the area of the resulting floorplan. An algorithm for general hierarchical floorplans is presented. The shape curves for non-slicing configurations are constructed by operations on the graph representations of the floorplan. The points of a shape curve are determined by simultaneously reducing the length of all longest paths of the vertical adjacency graph, using a minimum cut technique. The algorithm is applicable to hierarchical floorplans of high order and to modules with an infinite set of possible dimensions.",

keywords = "Shape, Iterative algorithms, Piecewise linear techniques, Algorithm design and analysis, Flexible printed circuits, Circuit topology, Heuristic algorithms, Approximation algorithms, Piecewise linear approximation",

author = "Khe-Sing The and D.F. Wong",

year = "1991",

month = oct,

day = "16",

doi = "10.1109/ICCD.1991.139963",

language = "English",

isbn = "0818622709",

series = "IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD",

publisher = "IEEE",

pages = "520--523",

booktitle = "[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors",

address = "United States",

note = "1991 IEEE International Conference on Computer Design, ICCD 1991 : VLSI in Computers and Processors ; Conference date: 14-10-1991 Through 16-10-1991",

url = "https://ieeexplore.ieee.org/xpl/conhome/367/proceeding",

}

The, K-S & Wong, DF 1991, Area optimization for higher order hierarchical floorplans. in [1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors. IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD, IEEE, pp. 520-523, 1991 IEEE International Conference on Computer Design, ICCD 1991, Cambridge, MA, United States, 14/10/91. https://doi.org/10.1109/ICCD.1991.139963

Area optimization for higher order hierarchical floorplans. / The, Khe-Sing; Wong, D.F.
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors. IEEE, 1991. p. 520-523 (IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD).

Research output: Chapter in book/report/conference proceeding › Conference proceeding

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AU - Wong, D.F.

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N2 - The floorplan area optimization problem is to determine the dimensions of each module when the topology of the floorplan is given. The objective is to minimize the area of the resulting floorplan. An algorithm for general hierarchical floorplans is presented. The shape curves for non-slicing configurations are constructed by operations on the graph representations of the floorplan. The points of a shape curve are determined by simultaneously reducing the length of all longest paths of the vertical adjacency graph, using a minimum cut technique. The algorithm is applicable to hierarchical floorplans of high order and to modules with an infinite set of possible dimensions.

AB - The floorplan area optimization problem is to determine the dimensions of each module when the topology of the floorplan is given. The objective is to minimize the area of the resulting floorplan. An algorithm for general hierarchical floorplans is presented. The shape curves for non-slicing configurations are constructed by operations on the graph representations of the floorplan. The points of a shape curve are determined by simultaneously reducing the length of all longest paths of the vertical adjacency graph, using a minimum cut technique. The algorithm is applicable to hierarchical floorplans of high order and to modules with an infinite set of possible dimensions.

KW - Shape

KW - Iterative algorithms

KW - Piecewise linear techniques

KW - Algorithm design and analysis

KW - Flexible printed circuits

KW - Circuit topology

KW - Heuristic algorithms

KW - Approximation algorithms

KW - Piecewise linear approximation

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T3 - IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD

SP - 520

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BT - [1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors

PB - IEEE

T2 - 1991 IEEE International Conference on Computer Design, ICCD 1991

Y2 - 14 October 1991 through 16 October 1991

ER -

Area optimization for higher order hierarchical floorplans

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