An exact tree-based structural technology mapping algorithm for configurable logic blocks in FPGAs

K. K. Lee; D. F. Wong

doi:10.1109/ICCD.1999.808428

An exact tree-based structural technology mapping algorithm for configurable logic blocks in FPGAs

K. K. Lee, D. F. Wong

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Research output: Chapter in book/report/conference proceeding › Conference proceeding › peer-review

2 Citations (Scopus)

Abstract

We consider technology mapping of combinational circuits onto complex configurable logic blocks (CLBs) with two levels of LUTs. We show that if the CLB has b bases, a tree network with n nodes call be mapped in O(C·n^2b-1) time, where C is a function dependent on b. b is fixed for a given CLB architecture. In particular, this algorithm runs in O(n⁵) time when mapping a circuit of n nodes onto the Xilinx XC4000. To the best of our knowledge, this is the first optimal polynomial time algorithm for mapping any non-trivial network onto such a complex CLB architecture. By simplifying the computation, we obtained an O(n³) algorithm. The mapping results are comparable to the best NP-hard MILP approach, but our algorithm runs in polynomial time and is much faster in practice. The larger MCNC benchmark circuits were mapped in a few minutes. Our algorithm also maps to CLBs with independent, heterogeneous LUTs as a special case.

Original language	English
Title of host publication	Proceedings of The 17th IEEE International Conference on Computer Design, ICCD 1999
Publisher	IEEE
Pages	216-221
Number of pages	6
ISBN (Print)	076950406X
DOIs	https://doi.org/10.1109/ICCD.1999.808428
Publication status	Published - 10 Oct 1999
Event	17th IEEE International Conference on Computer Design, ICCD 1999 - Austin, United States Duration: 10 Oct 1999 → 13 Oct 1999 https://ieeexplore.ieee.org/xpl/conhome/6554/proceeding (Conference proceedings)

Publication series

Name	Proceedings - IEEE International Conference on Computer Design (ICCD): VLSI in Computers and Processors
ISSN (Print)	1063-6404
ISSN (Electronic)	2576-6996

Conference

Conference	17th IEEE International Conference on Computer Design, ICCD 1999
Country/Territory	United States
City	Austin
Period	10/10/99 → 13/10/99
Internet address	https://ieeexplore.ieee.org/xpl/conhome/6554/proceeding (Conference proceedings)

Scopus Subject Areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ICCD.1999.808428

Cite this

Lee, K. K., & Wong, D. F. (1999). An exact tree-based structural technology mapping algorithm for configurable logic blocks in FPGAs. In Proceedings of The 17th IEEE International Conference on Computer Design, ICCD 1999 (pp. 216-221). (Proceedings - IEEE International Conference on Computer Design (ICCD): VLSI in Computers and Processors). IEEE. https://doi.org/10.1109/ICCD.1999.808428

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title = "An exact tree-based structural technology mapping algorithm for configurable logic blocks in FPGAs",

abstract = "We consider technology mapping of combinational circuits onto complex configurable logic blocks (CLBs) with two levels of LUTs. We show that if the CLB has b bases, a tree network with n nodes call be mapped in O(C·n2b-1) time, where C is a function dependent on b. b is fixed for a given CLB architecture. In particular, this algorithm runs in O(n5) time when mapping a circuit of n nodes onto the Xilinx XC4000. To the best of our knowledge, this is the first optimal polynomial time algorithm for mapping any non-trivial network onto such a complex CLB architecture. By simplifying the computation, we obtained an O(n3) algorithm. The mapping results are comparable to the best NP-hard MILP approach, but our algorithm runs in polynomial time and is much faster in practice. The larger MCNC benchmark circuits were mapped in a few minutes. Our algorithm also maps to CLBs with independent, heterogeneous LUTs as a special case.",

author = "Lee, {K. K.} and Wong, {D. F.}",

note = "This work was partially supported by the Texas Advanced Research Program under Grant No. 003658288; 17th IEEE International Conference on Computer Design, ICCD 1999 ; Conference date: 10-10-1999 Through 13-10-1999",

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series = "Proceedings - IEEE International Conference on Computer Design (ICCD): VLSI in Computers and Processors",

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Lee, KK & Wong, DF 1999, An exact tree-based structural technology mapping algorithm for configurable logic blocks in FPGAs. in Proceedings of The 17th IEEE International Conference on Computer Design, ICCD 1999. Proceedings - IEEE International Conference on Computer Design (ICCD): VLSI in Computers and Processors, IEEE, pp. 216-221, 17th IEEE International Conference on Computer Design, ICCD 1999, Austin, Texas, United States, 10/10/99. https://doi.org/10.1109/ICCD.1999.808428

An exact tree-based structural technology mapping algorithm for configurable logic blocks in FPGAs. / Lee, K. K.; Wong, D. F.
Proceedings of The 17th IEEE International Conference on Computer Design, ICCD 1999. IEEE, 1999. p. 216-221 (Proceedings - IEEE International Conference on Computer Design (ICCD): VLSI in Computers and Processors).

Research output: Chapter in book/report/conference proceeding › Conference proceeding › peer-review

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PY - 1999/10/10

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N2 - We consider technology mapping of combinational circuits onto complex configurable logic blocks (CLBs) with two levels of LUTs. We show that if the CLB has b bases, a tree network with n nodes call be mapped in O(C·n2b-1) time, where C is a function dependent on b. b is fixed for a given CLB architecture. In particular, this algorithm runs in O(n5) time when mapping a circuit of n nodes onto the Xilinx XC4000. To the best of our knowledge, this is the first optimal polynomial time algorithm for mapping any non-trivial network onto such a complex CLB architecture. By simplifying the computation, we obtained an O(n3) algorithm. The mapping results are comparable to the best NP-hard MILP approach, but our algorithm runs in polynomial time and is much faster in practice. The larger MCNC benchmark circuits were mapped in a few minutes. Our algorithm also maps to CLBs with independent, heterogeneous LUTs as a special case.

AB - We consider technology mapping of combinational circuits onto complex configurable logic blocks (CLBs) with two levels of LUTs. We show that if the CLB has b bases, a tree network with n nodes call be mapped in O(C·n2b-1) time, where C is a function dependent on b. b is fixed for a given CLB architecture. In particular, this algorithm runs in O(n5) time when mapping a circuit of n nodes onto the Xilinx XC4000. To the best of our knowledge, this is the first optimal polynomial time algorithm for mapping any non-trivial network onto such a complex CLB architecture. By simplifying the computation, we obtained an O(n3) algorithm. The mapping results are comparable to the best NP-hard MILP approach, but our algorithm runs in polynomial time and is much faster in practice. The larger MCNC benchmark circuits were mapped in a few minutes. Our algorithm also maps to CLBs with independent, heterogeneous LUTs as a special case.

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An exact tree-based structural technology mapping algorithm for configurable logic blocks in FPGAs

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