An exact gate decomposition algorithm for low-power technology mapping

Hai Zhou, D.F. Wong

Research output: Chapter in book/report/conference proceedingChapterpeer-review

7 Citations (Scopus)

Abstract

With the remarkable growth of portable application and the increasing frequency and integration density, power is being given comparable weight to speed and area in IC designs. In technology mapping, how decomposition is done can have a significant impact on the power dissipation of the final implementation. In the literature, only heuristic algorithms are given for the low-power gate decomposition problem. In this paper, we prove many properties an optimal decomposition tree must have. Based on these optimality properties, we design an efficient exact algorithm to solve the low-power gate decomposition problem. Moreover, the exact algorithm can be easily modified to a heuristic algorithm which performs much better than the known heuristics.
Original languageEnglish
Title of host publication1997 IEEE International Conference on Computer Aided Design, ICCAD 1997
PublisherIEEE
Pages575-580
Number of pages6
ISBN (Print)0818682000
DOIs
Publication statusPublished - Nov 1997
Event1997 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1997 - San Jose, United States
Duration: 9 Nov 199713 Nov 1997
https://ieeexplore.ieee.org/xpl/conhome/5191/proceeding (Link to conference proceedings)

Publication series

NameProceedings of IEEE International Conference on Computer Aided Design
PublisherIEEE

Conference

Conference1997 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1997
Country/TerritoryUnited States
CitySan Jose
Period9/11/9713/11/97
Internet address

Scopus Subject Areas

  • Software
  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design

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