Abstract
Shrinking transistor sizes, increasing circuit complexities, and high clock frequencies bring new board routing challenges that cannot be handled effectively by traditional routing algorithms. Many high-end designs in the industry today require manual routing efforts, which increases the design cycle times considerably. In this paper, we propose an escape routing algorithm to route nets within multiple dense components simultaneously so that the number of crossings in the intermediate area is minimized. We also show how to handle high-speed design constraints within the framework of this algorithm. Experimental comparisons with a recently proposed algorithm (Ozdal and Wong, 2004) show that our algorithm reduces the via requirements of industrial test cases on average by 39%.
Original language | English |
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Title of host publication | Proceedings of the 2005 International Conference on Computer-Aided Design |
Place of Publication | United States |
Publisher | IEEE |
Pages | 758-765 |
Number of pages | 8 |
ISBN (Print) | 078039254X, 9780780392540 |
DOIs | |
Publication status | Published - Nov 2005 |
Event | IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2005 - San Jose, United States Duration: 6 Nov 2005 → 10 Nov 2005 https://ieeexplore.ieee.org/xpl/conhome/10431/proceeding (Conference proceedings) |
Publication series
Name | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD |
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Volume | 2005 |
ISSN (Print) | 1092-3152 |
ISSN (Electronic) | 1558-2434 |
Conference
Conference | IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2005 |
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Country/Territory | United States |
City | San Jose |
Period | 6/11/05 → 10/11/05 |
Internet address |
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Scopus Subject Areas
- Software
- Computer Science Applications
- Computer Graphics and Computer-Aided Design