An enhanced bottom-up algorithm for floorplan design

Thomas R. Mueller; D. F. Wong; C. L. Liu

doi:10.1016/0167-9260(89)90036-9

An enhanced bottom-up algorithm for floorplan design

Thomas R. Mueller^*
, D. F. Wong
, C. L. Liu

^*Corresponding author for this work

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Research output: Contribution to journal › Journal article › peer-review

Abstract

We describe in this paper a fast algorithm for the design of floorplans. The algorithm can be used to carry out the complete design of a floorplan or to improve an existing floorplan. It is based on an enhanced bottom-up iterative improvement technique, and is capable of obtaining good solutions with an increase in speed of approximately two orders of magnitude over an algorithm using the method of simulated annealing.

Original language	English
Pages (from-to)	189-201
Number of pages	13
Journal	Integration, the VLSI Journal
Volume	7
Issue number	2
DOIs	https://doi.org/10.1016/0167-9260(89)90036-9
Publication status	Published - Aug 1989

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10.1016/0167-9260(89)90036-9

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title = "An enhanced bottom-up algorithm for floorplan design",

abstract = "We describe in this paper a fast algorithm for the design of floorplans. The algorithm can be used to carry out the complete design of a floorplan or to improve an existing floorplan. It is based on an enhanced bottom-up iterative improvement technique, and is capable of obtaining good solutions with an increase in speed of approximately two orders of magnitude over an algorithm using the method of simulated annealing.",

author = "Mueller, \{Thomas R.\} and Wong, \{D. F.\} and Liu, \{C. L.\}",

note = "Funding Information: This work was partially supported by the Semiconductor Research Corporation under contract 86-12-109, by the National Science Foundation under grant MIP 8703273, by a grant from the General Electric Company, by a grant from the Sandia Laboratories, and by the Texas Advanced Research Program under grant 4096. * * T.R. Mueller's work was carried out while he was a graduate student at the University of Illinois at Urbana-Champaign and was partially supported by a fellowship from the Tektronix Corporation. He is currently employed by AT\&T Bell Laboratories, NaperviUe, Illinois.",

year = "1989",

month = aug,

doi = "10.1016/0167-9260(89)90036-9",

language = "English",

volume = "7",

pages = "189--201",

journal = "Integration, the VLSI Journal",

issn = "0167-9260",

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T1 - An enhanced bottom-up algorithm for floorplan design

AU - Mueller, Thomas R.

AU - Wong, D. F.

AU - Liu, C. L.

N1 - Funding Information: This work was partially supported by the Semiconductor Research Corporation under contract 86-12-109, by the National Science Foundation under grant MIP 8703273, by a grant from the General Electric Company, by a grant from the Sandia Laboratories, and by the Texas Advanced Research Program under grant 4096. * * T.R. Mueller's work was carried out while he was a graduate student at the University of Illinois at Urbana-Champaign and was partially supported by a fellowship from the Tektronix Corporation. He is currently employed by AT&T Bell Laboratories, NaperviUe, Illinois.

PY - 1989/8

Y1 - 1989/8

N2 - We describe in this paper a fast algorithm for the design of floorplans. The algorithm can be used to carry out the complete design of a floorplan or to improve an existing floorplan. It is based on an enhanced bottom-up iterative improvement technique, and is capable of obtaining good solutions with an increase in speed of approximately two orders of magnitude over an algorithm using the method of simulated annealing.

AB - We describe in this paper a fast algorithm for the design of floorplans. The algorithm can be used to carry out the complete design of a floorplan or to improve an existing floorplan. It is based on an enhanced bottom-up iterative improvement technique, and is capable of obtaining good solutions with an increase in speed of approximately two orders of magnitude over an algorithm using the method of simulated annealing.

UR - https://www.scopus.com/pages/publications/45349111158

U2 - 10.1016/0167-9260(89)90036-9

DO - 10.1016/0167-9260(89)90036-9

M3 - Journal article

AN - SCOPUS:45349111158

SN - 0167-9260

VL - 7

SP - 189

EP - 201

JO - Integration, the VLSI Journal

JF - Integration, the VLSI Journal

IS - 2

ER -

An enhanced bottom-up algorithm for floorplan design

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