@article{4a2369232dd84a8db45f1498cbb0f7d4,
title = "An enhanced bottom-up algorithm for floorplan design",
abstract = "We describe in this paper a fast algorithm for the design of floorplans. The algorithm can be used to carry out the complete design of a floorplan or to improve an existing floorplan. It is based on an enhanced bottom-up iterative improvement technique, and is capable of obtaining good solutions with an increase in speed of approximately two orders of magnitude over an algorithm using the method of simulated annealing.",
author = "Mueller, {Thomas R.} and Wong, {D. F.} and Liu, {C. L.}",
note = "Funding Information: This work was partially supported by the Semiconductor Research Corporation under contract 86-12-109, by the National Science Foundation under grant MIP 8703273, by a grant from the General Electric Company, by a grant from the Sandia Laboratories, and by the Texas Advanced Research Program under grant 4096. * * T.R. Mueller's work was carried out while he was a graduate student at the University of Illinois at Urbana-Champaign and was partially supported by a fellowship from the Tektronix Corporation. He is currently employed by AT&T Bell Laboratories, NaperviUe, Illinois.",
year = "1989",
month = aug,
doi = "10.1016/0167-9260(89)90036-9",
language = "English",
volume = "7",
pages = "189--201",
journal = "Integration, the VLSI Journal",
issn = "0167-9260",
publisher = "Elsevier",
number = "2",
}