Abstract
We propose a novel buffer insertion algorithm for handling more general networks, whose underlying topology is a directed acyclic graph rather than just a RC tree. The algorithm finds a global buffering which minimizes buffer area while meeting the timing constraints. We use Lagrangian relaxation to translate the timing constraints to a cost in the objective function, and simplify the resulting objective function using the special structure of the problem we are solving. The core of the algorithm is a local refinement procedure, which iteratively computes the optimal buffering for each edge so as to minimize a weighted area and delay objective. The resulting procedure is fast, and takes full advantage of the slack available on noncritical paths.
Original language | English |
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Title of host publication | Proceedings of The 17th IEEE International Conference on Computer Design, ICCD 1999 |
Publisher | IEEE |
Pages | 210-215 |
Number of pages | 6 |
ISBN (Print) | 076950406X |
DOIs | |
Publication status | Published - 10 Oct 1999 |
Event | 17th IEEE International Conference on Computer Design, ICCD 1999 - Austin, United States Duration: 10 Oct 1999 → 13 Oct 1999 https://ieeexplore.ieee.org/xpl/conhome/6554/proceeding (Conference proceedings) |
Publication series
Name | Proceedings - IEEE International Conference on Computer Design (ICCD): VLSI in Computers and Processors |
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Volume | 1999-October |
ISSN (Print) | 1063-6404 |
ISSN (Electronic) | 2576-6996 |
Conference
Conference | 17th IEEE International Conference on Computer Design, ICCD 1999 |
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Country/Territory | United States |
City | Austin |
Period | 10/10/99 → 13/10/99 |
Internet address |
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Scopus Subject Areas
- Hardware and Architecture
- Electrical and Electronic Engineering